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authorMatt DeVillier <matt.devillier@gmail.com>2020-02-26 13:06:01 -0600
committerPatrick Georgi <pgeorgi@google.com>2020-03-16 14:42:30 +0000
commit75afc79aae192629c66e0472a6f365f566be8412 (patch)
tree343dd8243f28d46baeb6ccfc1e538159da75e58b /src
parent6d6fb6bdd2c3fe5f198bb37c51609b4768c7fd74 (diff)
downloadcoreboot-75afc79aae192629c66e0472a6f365f566be8412.tar.xz
mb/51nb/x210: update devicetree
- Add USB ports for SD card reader, fingerprint reader, and internal port. - Enable PcieRpClkReqSupport on NVMe root port, correct values for ClkReq/ClkSrc. - Improve comment for M.2-2230 USB port (BT) Parts derived from x210_test branch of HarryKipper's repo: https://github.com/harrykipper/coreboot Change-Id: Ib64629ada4726e5edc080608f71a51f56a9b747c Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39143 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/51nb/x210/devicetree.cb11
1 files changed, 7 insertions, 4 deletions
diff --git a/src/mainboard/51nb/x210/devicetree.cb b/src/mainboard/51nb/x210/devicetree.cb
index 6bfbe1d879..ee6e5ffd59 100644
--- a/src/mainboard/51nb/x210/devicetree.cb
+++ b/src/mainboard/51nb/x210/devicetree.cb
@@ -99,17 +99,20 @@ chip soc/intel/skylake
register "PcieRpLtrEnable[3]" = "1"
register "PcieRpEnable[8]" = "1" # NVMe controller
- register "PcieRpClkReqSupport[8]" = "0"
- register "PcieRpClkReqNumber[8]" = "2"
- register "PcieRpClkSrcNumber[8]" = "2"
+ register "PcieRpClkReqSupport[8]" = "1"
+ register "PcieRpClkReqNumber[8]" = "4"
+ register "PcieRpClkSrcNumber[8]" = "4"
register "PcieRpAdvancedErrorReporting[8]" = "1"
register "PcieRpLtrEnable[8]" = "1"
register "usb2_ports[0]" = "USB2_PORT_MID(OC1)" # Type-A Port (left)
register "usb2_ports[1]" = "USB2_PORT_MID(OC1)" # Type-A Port (left)
+ register "usb2_ports[2]" = "USB2_PORT_FLEX(OC1)" # FPR
+ register "usb2_ports[3]" = "USB2_PORT_FLEX(OC1)" # SD
+ register "usb2_ports[4]" = "USB2_PORT_FLEX(OC1)" # INT
register "usb2_ports[5]" = "USB2_PORT_MID(OC1)" # Type-A Port (right)
register "usb2_ports[6]" = "USB2_PORT_FLEX(OC2)" # Webcam
- register "usb2_ports[7]" = "USB2_PORT_FLEX(OC2)" # WiFi PCIe port USB
+ register "usb2_ports[7]" = "USB2_PORT_FLEX(OC2)" # M.2-2230 USB (BT)
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port (left)
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port (left)