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authorArthur Heymans <arthur@aheymans.xyz>2019-01-07 15:10:57 +0100
committerPatrick Georgi <pgeorgi@google.com>2019-01-14 12:09:41 +0000
commit786a1fec27824632dc441582b5edb2cf9305a1b5 (patch)
tree4efa55e8ed122b5b83ecc1af3e3cd6759515831f /src
parent48bf712d359451c9c754f2713be2268eddb19035 (diff)
downloadcoreboot-786a1fec27824632dc441582b5edb2cf9305a1b5.tar.xz
cpu/intel/gen1/smmrelocate: Check for sanity on SMRR
This happens when TSEG is found to be unaligned. Change-Id: Id0c078a880dddb55857af2bca233cf4dee91250a Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30709 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
-rw-r--r--src/cpu/intel/smm/gen1/smmrelocate.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/cpu/intel/smm/gen1/smmrelocate.c b/src/cpu/intel/smm/gen1/smmrelocate.c
index 426eae5eab..5667648d24 100644
--- a/src/cpu/intel/smm/gen1/smmrelocate.c
+++ b/src/cpu/intel/smm/gen1/smmrelocate.c
@@ -132,7 +132,7 @@ static void asmlinkage cpu_smm_do_relocation(void *arg)
/* Write SMRR MSRs based on indicated support. */
mtrr_cap = rdmsr(MTRR_CAP_MSR);
- if (mtrr_cap.lo & SMRR_SUPPORTED)
+ if (mtrr_cap.lo & SMRR_SUPPORTED && relo_params->smrr_mask.lo != 0)
write_smrr(relo_params);
southbridge_clear_smi_status();