summaryrefslogtreecommitdiff
path: root/src
diff options
context:
space:
mode:
authorDuncan Laurie <dlaurie@chromium.org>2013-07-30 15:45:25 -0700
committerRonald G. Minnich <rminnich@gmail.com>2013-12-18 02:24:13 +0100
commit7d14e89c54e89901e7196e7a5da9583515576128 (patch)
tree27a4b9964790b67706a94ea10a7772056a182899 /src
parentb1ae0303ce1ae3cb7f5b4f9ded32fac424be5bcb (diff)
downloadcoreboot-7d14e89c54e89901e7196e7a5da9583515576128.tar.xz
lynxpoint: Don't write to non-existent EHCI
The LynxPoint-LP chipset only has one EHCI controller so we should not attempt to write into the second one that only exists on LynxPoint-H. Change-Id: I1eae060c7f0a5873c9684e5abfeea5cb5895ab62 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/63799 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4405 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src')
-rw-r--r--src/southbridge/intel/lynxpoint/early_pch.c6
-rw-r--r--src/southbridge/intel/lynxpoint/early_usb.c5
2 files changed, 8 insertions, 3 deletions
diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c
index 38506c9438..9909bb6d44 100644
--- a/src/southbridge/intel/lynxpoint/early_pch.c
+++ b/src/southbridge/intel/lynxpoint/early_pch.c
@@ -42,6 +42,12 @@ const struct rcba_config_instruction pch_early_config[] = {
RCBA_END_CONFIG,
};
+int pch_is_lp(void)
+{
+ u8 id = pci_read_config8(PCH_LPC_DEV, PCI_DEVICE_ID + 1);
+ return id == PCH_TYPE_LPT_LP;
+}
+
static void pch_enable_bars(void)
{
/* Setting up Southbridge. In the northbridge code. */
diff --git a/src/southbridge/intel/lynxpoint/early_usb.c b/src/southbridge/intel/lynxpoint/early_usb.c
index 9a1a4cb35e..d328ef6818 100644
--- a/src/southbridge/intel/lynxpoint/early_usb.c
+++ b/src/southbridge/intel/lynxpoint/early_usb.c
@@ -54,7 +54,6 @@ static void enable_usb_bar_on_device(device_t dev, u32 bar)
void enable_usb_bar(void)
{
enable_usb_bar_on_device(PCH_EHCI1_DEV, PCH_EHCI1_TEMP_BAR0);
-#if !CONFIG_INTEL_LYNXPOINT_LP
- enable_usb_bar_on_device(PCH_EHCI2_DEV, PCH_EHCI2_TEMP_BAR0);
-#endif
+ if (!pch_is_lp())
+ enable_usb_bar_on_device(PCH_EHCI2_DEV, PCH_EHCI2_TEMP_BAR0);
}