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authorMarc Jones <marcj303@gmail.com>2017-02-23 22:06:01 -0700
committerMarc Jones <marc@marcjonesconsulting.com>2017-04-25 06:15:46 +0200
commit7e438af99575365a97f87f59e83e1224571ac5c2 (patch)
treec61f822a1c22a422a81577cce5c65888aac544a9 /src
parentefd077ac5283cb88627a53b703f1eb67aec4e5a3 (diff)
downloadcoreboot-7e438af99575365a97f87f59e83e1224571ac5c2.tar.xz
mainboard/amd/gardenia: Remove PMxEE write on S4 resume
Delete the write to PM register 0xee. This register is not listed in the current BKDG and S4 is not currently supported on this APU. NDA document #47517 "A55/.../A85X fusion Controller Hub Register Reference Guide" provides some clues on the intent of this write. This register has always been observed to power on with a value of 0x08 so the write has no effect. This should be revisited again when SMI and PSP fully implement the support required for S3. Change-Id: I35e6c5f7ad1de7f51b018543d2f7ce82182f11e4 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/18494 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/amd/gardenia/romstage.c5
1 files changed, 0 insertions, 5 deletions
diff --git a/src/mainboard/amd/gardenia/romstage.c b/src/mainboard/amd/gardenia/romstage.c
index 0136a98344..75674a090a 100644
--- a/src/mainboard/amd/gardenia/romstage.c
+++ b/src/mainboard/amd/gardenia/romstage.c
@@ -66,11 +66,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* TODO: Disable cache is not ok. */
disable_cache_as_ram();
- if (acpi_is_wakeup_s4()) {
- outb(0xEE, PM_INDEX);
- outb(0x8, PM_DATA);
- }
-
post_code(0x50);
copy_and_run();