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authorMarshall Dawson <marshalldawson3rd@gmail.com>2017-10-20 12:36:35 -0600
committerAaron Durbin <adurbin@chromium.org>2018-02-16 22:38:58 +0000
commit82145a1275e36e8ed528ab58f812d5e634b9c574 (patch)
tree76d6831317a8b91a35e0d54f058dc4ffb83ed185 /src
parentc0dbedac431a2038cd7382d4c0cd8ccb958675ac (diff)
downloadcoreboot-82145a1275e36e8ed528ab58f812d5e634b9c574.tar.xz
amd/stoneyridge: Use generic fixed MTRR setup
Add the X86_AMD_FIXED_MTRRS select back to Kconfig. This got lost when stoneyridge was converted from a cpu/northbridge/southbridge implementation to soc/. Remove the setup from model_15_init.c because this is duplicated functionality. BUG=b:68019051 TEST=Boot Kahlee, check steps with HDT Change-Id: Id5526dcff12555efccab811fa3442ba1bff051bb Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/23723 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src')
-rw-r--r--src/soc/amd/stoneyridge/Kconfig1
-rw-r--r--src/soc/amd/stoneyridge/model_15_init.c37
2 files changed, 1 insertions, 37 deletions
diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig
index 8bf577c72f..de1cb927ab 100644
--- a/src/soc/amd/stoneyridge/Kconfig
+++ b/src/soc/amd/stoneyridge/Kconfig
@@ -31,6 +31,7 @@ config CPU_SPECIFIC_OPTIONS
select ARCH_VERSTAGE_X86_32
select ARCH_ROMSTAGE_X86_32
select ARCH_RAMSTAGE_X86_32
+ select X86_AMD_FIXED_MTRRS
select ACPI_AMD_HARDWARE_SLEEP_VALUES
select COLLECT_TIMESTAMPS_NO_TSC
select DRIVERS_I2C_DESIGNWARE
diff --git a/src/soc/amd/stoneyridge/model_15_init.c b/src/soc/amd/stoneyridge/model_15_init.c
index 4bde81eb51..83fadd0e1f 100644
--- a/src/soc/amd/stoneyridge/model_15_init.c
+++ b/src/soc/amd/stoneyridge/model_15_init.c
@@ -16,7 +16,6 @@
#include <console/console.h>
#include <cpu/x86/lapic.h>
#include <cpu/x86/msr.h>
-#include <cpu/amd/mtrr.h>
#include <device/device.h>
#include <device/pci.h>
#include <string.h>
@@ -26,22 +25,9 @@
#include <cpu/cpu.h>
#include <cpu/x86/cache.h>
-#include <cpu/x86/mtrr.h>
#include <cpu/amd/amdfam15.h>
#include <arch/acpi.h>
-static void msr_rw_dram(unsigned int reg)
-{
-#define RW_DRAM (MTRR_READ_MEM | MTRR_WRITE_MEM)
-#define ALL_RW_DRAM ((RW_DRAM << 24) | (RW_DRAM << 16) | \
- (RW_DRAM << 8) | (RW_DRAM))
-
- msr_t mtrr = rdmsr(reg);
- mtrr.hi |= ALL_RW_DRAM;
- mtrr.lo |= ALL_RW_DRAM;
- wrmsr(reg, mtrr);
-}
-
static void model_15_init(device_t dev)
{
printk(BIOS_DEBUG, "Model 15 Init.\n");
@@ -49,29 +35,6 @@ static void model_15_init(device_t dev)
int i;
msr_t msr;
- disable_cache();
-
- /* Enable access to AMD RdDram and WrDram extension bits */
- msr = rdmsr(SYSCFG_MSR);
- msr.lo |= SYSCFG_MSR_MtrrFixDramModEn;
- msr.lo &= ~SYSCFG_MSR_MtrrFixDramEn;
- wrmsr(SYSCFG_MSR, msr);
-
- /* Send all but A0000-BFFFF to DRAM */
- msr_rw_dram(MTRR_FIX_64K_00000);
- msr_rw_dram(MTRR_FIX_16K_80000);
- for (i = MTRR_FIX_4K_C0000 ; i <= MTRR_FIX_4K_F8000 ; i++)
- msr_rw_dram(i);
-
- /* Hide RdDram and WrDram bits, and clear Tom2ForceMemTypeWB */
- msr = rdmsr(SYSCFG_MSR);
- msr.lo &= ~SYSCFG_MSR_TOM2WB;
- msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn;
- msr.lo |= SYSCFG_MSR_MtrrFixDramEn;
- wrmsr(SYSCFG_MSR, msr);
-
- x86_enable_cache();
-
/* zero the machine check error status registers */
msr.lo = 0;
msr.hi = 0;