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authorWenkai Du <wenkai.du@intel.com>2014-12-05 14:00:26 -0800
committerStefan Reinauer <stefan.reinauer@coreboot.org>2015-04-10 20:09:56 +0200
commit83067610f754f89025bf781cdf8857135e946b03 (patch)
tree9464b44d722b963b6c1f6bdc85299218219d6a8c /src
parentb75fb0acda99e804b5049ff75f3a51454fb7ba2c (diff)
downloadcoreboot-83067610f754f89025bf781cdf8857135e946b03.tar.xz
broadwell: Fix PCIe ports programming sequences to enable HSIOPC
HSIOPC/GPIO71 is used to control power to VCCHSIO, VCCUSB3PLL and VCCSATA3PLL in S0. PCH will drive HSIOPC low when all the high speed I/O controllers (xHCI, SATA, GbE and PCIe) are idle. This patch added a few additional PCIe programming steps as required in 535127 BIOS Writer Guide Rev 2.3.0 to enable this power saving mode. BUG=none BRANCH=none TEST=tested on Paine watching GPIO71 toggling as expected Change-Id: Ica6954c125ec3129e2659168f1f23dc861ce5708 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: e38f9ef57c480ca5ee420020eb80a1adb3c381d3 Original-Change-Id: I88ef125c681c8631e8b887f7ccf017b90b8c0f10 Original-Signed-off-by: Wenkai Du <wenkai.du@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/238580 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/9482 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src')
-rw-r--r--src/soc/intel/broadwell/pcie.c23
-rw-r--r--src/soc/intel/broadwell/romstage/pch.c15
2 files changed, 33 insertions, 5 deletions
diff --git a/src/soc/intel/broadwell/pcie.c b/src/soc/intel/broadwell/pcie.c
index bb237be21f..4476fe4f65 100644
--- a/src/soc/intel/broadwell/pcie.c
+++ b/src/soc/intel/broadwell/pcie.c
@@ -32,6 +32,7 @@
#include <soc/rcba.h>
#include <soc/intel/broadwell/chip.h>
#include <soc/cpu.h>
+#include <delay.h>
static void pcie_update_cfg8(device_t dev, int reg, u8 mask, u8 or);
static void pcie_update_cfg(device_t dev, int reg, u32 mask, u32 or);
@@ -300,6 +301,7 @@ static void root_port_commit_config(void)
for (i = 0; i < rpc.num_ports; i++) {
device_t dev;
u32 reg32;
+ int n = 0;
dev = rpc.ports[i];
@@ -313,11 +315,22 @@ static void root_port_commit_config(void)
printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev));
- /* Ensure memory, io, and bus master are all disabled */
- reg32 = pci_read_config32(dev, PCI_COMMAND);
- reg32 &= ~(PCI_COMMAND_MASTER |
- PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
- pci_write_config32(dev, PCI_COMMAND, reg32);
+ /* 8.2 Configuration of PCI Express Root Ports */
+ pcie_update_cfg(dev, 0x338, ~(1 << 26), 1 << 26);
+
+ do {
+ reg32 = pci_read_config32(dev, 0x328);
+ n++;
+ if (((reg32 & 0xff000000) == 0x01000000) || (n > 500))
+ break;
+ udelay(100);
+ } while (1);
+
+ if (n > 500)
+ printk(BIOS_DEBUG, "%s: Timeout waiting for 328h\n",
+ dev_path(dev));
+
+ pcie_update_cfg(dev, 0x408, ~(1 << 27), 1 << 27);
/* Disable this device if possible */
pch_disable_devfn(dev);
diff --git a/src/soc/intel/broadwell/romstage/pch.c b/src/soc/intel/broadwell/romstage/pch.c
index f31e6baa76..6fa6c395e2 100644
--- a/src/soc/intel/broadwell/romstage/pch.c
+++ b/src/soc/intel/broadwell/romstage/pch.c
@@ -135,6 +135,16 @@ static void pch_enable_lpc(void)
pci_write_config32(PCH_DEV_LPC, LPC_GEN4_DEC, config->gen4_dec);
}
+static void pcie_update_cfg(device_t dev, int reg, u32 mask, u32 or)
+{
+ u32 reg32;
+
+ reg32 = pci_read_config32(dev, reg);
+ reg32 &= mask;
+ reg32 |= or;
+ pci_write_config32(dev, reg, reg32);
+}
+
void pch_early_init(void)
{
reg_script_run_on_dev(PCH_DEV_LPC, pch_early_init_script);
@@ -143,4 +153,9 @@ void pch_early_init(void)
pch_enable_lpc();
enable_smbus();
+
+ /* 8.14 Additional PCI Express Programming Steps, step #1 */
+ pcie_update_cfg(_PCH_DEV(PCIE, 0), 0xf4, ~0x60, 0);
+ pcie_update_cfg(_PCH_DEV(PCIE, 0), 0xf4, ~0x80, 0x80);
+ pcie_update_cfg(_PCH_DEV(PCIE, 0), 0xe2, ~0x30, 0x30);
}