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authorElyes HAOUAS <ehaouas@noos.fr>2018-01-19 12:52:25 +0100
committerMartin Roth <martinroth@google.com>2018-01-23 05:19:31 +0000
commit8324d87bf4f8900971be5584f11110dc261f14e5 (patch)
tree41201a80178b2977e178a8d84c25702206821483 /src
parent36e809ffd61f39da657023e3a7278616ecc4dfb7 (diff)
downloadcoreboot-8324d87bf4f8900971be5584f11110dc261f14e5.tar.xz
nb/intel/i945: Use ESMRAMC instead of 0x9e
Macro renamed to be in accordance with the name used in the datasheet. Change-Id: I5671c39608769b2c5ea2fb17809430f56e5f0b71 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/23330 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src')
-rw-r--r--src/northbridge/intel/i945/i945.h2
-rw-r--r--src/northbridge/intel/i945/northbridge.c2
-rw-r--r--src/northbridge/intel/i945/ram_calc.c2
3 files changed, 3 insertions, 3 deletions
diff --git a/src/northbridge/intel/i945/i945.h b/src/northbridge/intel/i945/i945.h
index 330ace1bed..5929a1d01c 100644
--- a/src/northbridge/intel/i945/i945.h
+++ b/src/northbridge/intel/i945/i945.h
@@ -75,7 +75,7 @@
#define LAC 0x97 /* Legacy Access Control */
#define TOLUD 0x9c /* Top of Low Used Memory */
#define SMRAM 0x9d /* System Management RAM Control */
-#define ESMRAM 0x9e /* Extended System Management RAM Control */
+#define ESMRAMC 0x9e /* Extended System Management RAM Control */
#define TOM 0xa0
diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c
index 57f4388506..fdb37b1d47 100644
--- a/src/northbridge/intel/i945/northbridge.c
+++ b/src/northbridge/intel/i945/northbridge.c
@@ -95,7 +95,7 @@ static void pci_domain_set_resources(device_t dev)
uma_memory_size = uma_size * 1024ULL;
}
- reg8 = pci_read_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), 0x9e);
+ reg8 = pci_read_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), ESMRAMC);
if (reg8 & 1) {
int tseg_size = 0;
printk(BIOS_DEBUG, "TSEG decoded, subtracting ");
diff --git a/src/northbridge/intel/i945/ram_calc.c b/src/northbridge/intel/i945/ram_calc.c
index 0c337bb54e..990df972e2 100644
--- a/src/northbridge/intel/i945/ram_calc.c
+++ b/src/northbridge/intel/i945/ram_calc.c
@@ -36,7 +36,7 @@ static uintptr_t smm_region_start(void)
tom = (pci_read_config8(PCI_DEV(0, 0, 0), TOLUD) & 0xf7) << 24;
/* if TSEG enabled subtract size */
- switch (pci_read_config8(PCI_DEV(0, 0, 0), ESMRAM) & 0x07) {
+ switch (pci_read_config8(PCI_DEV(0, 0, 0), ESMRAMC) & 0x07) {
case 0x01:
/* 1MB TSEG */
tom -= 0x100000;