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authorAndrey Petrov <andrey.petrov@intel.com>2016-07-14 09:52:00 -0700
committerAaron Durbin <adurbin@chromium.org>2016-07-15 18:21:54 +0200
commit89e7b49a114f60f2fddf5f409dea0025785d4604 (patch)
treeafefa7d92b76026ee6da60119cd23430b78272e4 /src
parentd779605c29a1630a256c8a1c4966214c580481ec (diff)
downloadcoreboot-89e7b49a114f60f2fddf5f409dea0025785d4604.tar.xz
soc/intel/apollolake: Consolidate ISH enabling
Since the Integrated Sensor Hub can be disabled through devicetree.cb as a PCI device, there is no need for a separate register variable. Remove handling the register and update mainboards' devicetrees. Also keep ISH disabled on both Reef and Amenia. Change-Id: I90dbf57b353ae1b80295ecf39877b10ed21de146 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/15710 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/google/reef/devicetree.cb7
-rw-r--r--src/mainboard/intel/amenia/devicetree.cb5
-rw-r--r--src/soc/intel/apollolake/chip.c2
-rw-r--r--src/soc/intel/apollolake/chip.h3
4 files changed, 2 insertions, 15 deletions
diff --git a/src/mainboard/google/reef/devicetree.cb b/src/mainboard/google/reef/devicetree.cb
index 3425c432b3..34f0b03f52 100644
--- a/src/mainboard/google/reef/devicetree.cb
+++ b/src/mainboard/google/reef/devicetree.cb
@@ -6,11 +6,6 @@ chip soc/intel/apollolake
register "pcie_rp4_clkreq_pin" = "0" # wifi/bt
- # TODO(furquan): Remove this once global reset issue is fixed in later
- # steppings.
- # Integrated Sensor Hub
- register "integrated_sensor_hub_enable" = "1"
-
# EMMC TX DATA Delay 1#
# 0x0C[14:8] stands for 12*125 = 1500 pSec delay for HS400
# 0x11[6:0] stands for 17*125 = 2125 pSec delay for SDR104/HS200
@@ -61,7 +56,7 @@ chip soc/intel/apollolake
device generic 0 on end
end
end
- device pci 11.0 on end # - ISH
+ device pci 11.0 off end # - ISH
device pci 12.0 off end # - SATA
device pci 13.0 off end # - Root Port 2 - PCIe-A 0
device pci 13.1 off end # - Root Port 3 - PCIe-A 1
diff --git a/src/mainboard/intel/amenia/devicetree.cb b/src/mainboard/intel/amenia/devicetree.cb
index 3f5873e784..8f15c83523 100644
--- a/src/mainboard/intel/amenia/devicetree.cb
+++ b/src/mainboard/intel/amenia/devicetree.cb
@@ -7,9 +7,6 @@ chip soc/intel/apollolake
register "pcie_rp0_clkreq_pin" = "3" # wifi/bt
register "pcie_rp2_clkreq_pin" = "0" # SSD
- # Integrated Sensor Hub
- register "integrated_sensor_hub_enable" = "0"
-
# EMMC TX DATA Delay 1#
# 0x1A[14:8] stands for 26*125 = 3250 pSec delay for HS400
# 0x1A[6:0] stands for 26*125 = 3250 pSec delay for SDR104/HS200
@@ -43,7 +40,7 @@ chip soc/intel/apollolake
device generic 0 on end
end
end
- device pci 11.0 on end # - ISH
+ device pci 11.0 off end # - ISH
device pci 12.0 on end # - SATA
device pci 13.0 off end # - PCIe-A 0
device pci 13.1 off end # - PCIe-A 1
diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c
index 9d08c57015..accc1bb1d0 100644
--- a/src/soc/intel/apollolake/chip.c
+++ b/src/soc/intel/apollolake/chip.c
@@ -396,8 +396,6 @@ void platform_fsp_silicon_init_params_cb(struct FSPS_UPD *silupd)
if (cfg->emmc_rx_cmd_data_cntl2 != 0)
silconfig->EmmcRxCmdDataCntl2 = cfg->emmc_rx_cmd_data_cntl2;
- silconfig->IshEnable = cfg->integrated_sensor_hub_enable;
-
silconfig->LPSS_S0ixEnable = cfg->lpss_s0ix_enable;
/* Disable setting of EISS bit in FSP. */
diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h
index bcc81070a9..a1df4810ca 100644
--- a/src/soc/intel/apollolake/chip.h
+++ b/src/soc/intel/apollolake/chip.h
@@ -93,9 +93,6 @@ struct soc_intel_apollolake_config {
/* Configure serial IRQ (SERIRQ) line. */
enum serirq_mode serirq_mode;
- /* Integrated Sensor Hub */
- uint8_t integrated_sensor_hub_enable;
-
/* I2C bus configuration */
struct apollolake_i2c_config i2c[APOLLOLAKE_I2C_DEV_MAX];