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| author | Dave Frodin <dave.frodin@se-eng.com> | 2013-04-17 18:21:09 -0600 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2013-04-18 18:35:12 +0200 |
| commit | 8a6f7a77f3ab169480b8d22caf1a8d70e3188c62 (patch) | |
| tree | 499cc3e546a211f04fbd84519c5dd2be72fdb9de /src | |
| parent | 6ceed0929d1e11c9d8807427750bb6e4f14806fd (diff) | |
| download | coreboot-8a6f7a77f3ab169480b8d22caf1a8d70e3188c62.tar.xz | |
AMD/SB800: Define the GPP PCIe lane distribution
Commit 23023a5 correctly enabled the SB800 GPP PCIe ports but didn't
distribute the 4 GPP PCIe lanes amongst the enabled PCIe ports.
This fix was verified by openvoid on a AsRock E350M1 motherboard.
Change-Id: I0116c5f518e0d000be609013446e53da4112f586
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/3104
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/southbridge/amd/cimx/sb800/late.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c index cfdf9f2a40..74b2d089eb 100644 --- a/src/southbridge/amd/cimx/sb800/late.c +++ b/src/southbridge/amd/cimx/sb800/late.c @@ -368,13 +368,13 @@ static void sb800_enable(device_t dev) /* the first sb800 device */ switch (GPP_CFGMODE) { /* config the GPP PCIe ports */ case GPP_CFGMODE_X2200: - abcfg_reg(0xc0, 0x01FF, 0x030); /* x2 Port_0, x2 Port_1 */ + abcfg_reg(0xc0, 0x01FF, 0x032); /* x2 Port_0, x2 Port_1 */ break; case GPP_CFGMODE_X2110: - abcfg_reg(0xc0, 0x01FF, 0x070); /* x2 Port_0, x1 Port_1&2 */ + abcfg_reg(0xc0, 0x01FF, 0x073); /* x2 Port_0, x1 Port_1&2 */ break; case GPP_CFGMODE_X1111: - abcfg_reg(0xc0, 0x01FF, 0x0F0); /* x1 Port_0&1&2&3 */ + abcfg_reg(0xc0, 0x01FF, 0x0F4); /* x1 Port_0&1&2&3 */ break; case GPP_CFGMODE_X4000: default: |