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authorAndre Heider <a.heider@gmail.com>2018-02-16 12:44:11 +0100
committerMartin Roth <martinroth@google.com>2018-02-20 20:36:33 +0000
commit92712d361d0ecdd33d5fb097630b0b61e96ab5bd (patch)
tree724a447678752703f7eb7feb7990f8ae05b360b4 /src
parent86fd16cc0b755fb874777b7da61076322f903805 (diff)
downloadcoreboot-92712d361d0ecdd33d5fb097630b0b61e96ab5bd.tar.xz
soc/nvidia/tegra210: set up the clock of the chosen UART
Don't always set up UARTA, but instead honor CONFIG_CONSOLE_SERIAL_TEGRA210_UARTx and set up the clock of the chosen UART. Now the matching clock for the used UART is set up. (The UART driver uses CONFIG_CONSOLE_SERIAL_TEGRA210_UART_ADDRESS, which in return is already based on CONFIG_CONSOLE_SERIAL_TEGRA210_UARTx.) Change-Id: Ife209d42af83459136a019c21c2a069396ab36db Signed-off-by: Andre Heider <a.heider@gmail.com> Reviewed-on: https://review.coreboot.org/23796 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Julius Werner <jwerner@chromium.org>
Diffstat (limited to 'src')
-rw-r--r--src/soc/nvidia/tegra210/clock.c10
1 files changed, 7 insertions, 3 deletions
diff --git a/src/soc/nvidia/tegra210/clock.c b/src/soc/nvidia/tegra210/clock.c
index cc8af55761..ba1efdc000 100644
--- a/src/soc/nvidia/tegra210/clock.c
+++ b/src/soc/nvidia/tegra210/clock.c
@@ -21,6 +21,7 @@
#include <soc/clk_rst.h>
#include <soc/clock.h>
#include <soc/clst_clk.h>
+#include <soc/console_uart.h>
#include <soc/flow.h>
#include <soc/maincpu.h>
#include <soc/pmc.h>
@@ -489,12 +490,15 @@ u32 clock_configure_plld(u32 frequency)
*/
void clock_early_uart(void)
{
- write32(CLK_RST_REG(clk_src_uarta),
- CLK_SRC_DEV_ID(UARTA, PLLP) << CLK_SOURCE_SHIFT |
+ if (console_uart_get_id() == UART_ID_NONE)
+ return;
+
+ write32(console_uart_clk_rst_reg(),
+ console_uart_clk_src_dev_id() << CLK_SOURCE_SHIFT |
CLK_UART_DIV_OVERRIDE |
CLK_DIVIDER(TEGRA_PLLP_KHZ, 1843));
- clock_enable_clear_reset_l(CLK_L_UARTA);
+ console_uart_clock_enable_clear_reset();
}
/* Enable output clock (CLK1~3) for external peripherals. */