diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2019-10-12 18:06:46 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-10-28 11:59:03 +0000 |
| commit | 942ad6a137027d6a7d8d082dee20bb64c81dc813 (patch) | |
| tree | ed6be2c5c998a308eee157c7b740cd5563d29c24 /src | |
| parent | 947916eb2d2648c1cf605a6c660b705876835ea5 (diff) | |
| download | coreboot-942ad6a137027d6a7d8d082dee20bb64c81dc813.tar.xz | |
cpu/intel/car: Correctly cache the bootblock with C_ENVIRONMENT_BOOTBLOCK
With CONFIG_C_ENVIRONMENT_BOOTBLOCK it makes more sense to rely on the
size of the bootblock over CONFIG_XIP_ROM_SIZE. To make this work,
only powers of 2 are allowed as bootblock size.
Change-Id: Ic8104ca9c51e4d2eccdb277e4c2111d2da662f3e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35990
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src')
| -rw-r--r-- | src/cpu/intel/car/core2/cache_as_ram.S | 13 | ||||
| -rw-r--r-- | src/cpu/intel/car/p3/cache_as_ram.S | 13 | ||||
| -rw-r--r-- | src/cpu/intel/car/p4-netburst/cache_as_ram.S | 13 |
3 files changed, 33 insertions, 6 deletions
diff --git a/src/cpu/intel/car/core2/cache_as_ram.S b/src/cpu/intel/car/core2/cache_as_ram.S index f8fa806125..a1bec12ede 100644 --- a/src/cpu/intel/car/core2/cache_as_ram.S +++ b/src/cpu/intel/car/core2/cache_as_ram.S @@ -18,6 +18,15 @@ #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE +#if CONFIG(C_ENVIRONMENT_BOOTBLOCK) +#if ((CONFIG_C_ENV_BOOTBLOCK_SIZE & (CONFIG_C_ENV_BOOTBLOCK_SIZE - 1)) != 0) +#error "CONFIG_C_ENV_BOOTBLOCK_SIZE must be a power of 2!" +#endif +#define XIP_ROM_SIZE CONFIG_C_ENV_BOOTBLOCK_SIZE +#else +#define XIP_ROM_SIZE CONFIG_XIP_ROM_SIZE +#endif + .global bootblock_pre_c_entry .code32 @@ -148,13 +157,13 @@ addrsize_set_high: * https://mail.coreboot.org/pipermail/coreboot/2010-October/060922.html */ movl $_program, %eax - andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax + andl $(~(XIP_ROM_SIZE - 1)), %eax orl $MTRR_TYPE_WRPROT, %eax wrmsr movl $MTRR_PHYS_MASK(1), %ecx rdmsr - movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax + movl $(~(XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax wrmsr post_code(0x28) diff --git a/src/cpu/intel/car/p3/cache_as_ram.S b/src/cpu/intel/car/p3/cache_as_ram.S index 9a7dc5f256..33f0bfd2a3 100644 --- a/src/cpu/intel/car/p3/cache_as_ram.S +++ b/src/cpu/intel/car/p3/cache_as_ram.S @@ -18,6 +18,15 @@ #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE +#if CONFIG(C_ENVIRONMENT_BOOTBLOCK) +#if ((CONFIG_C_ENV_BOOTBLOCK_SIZE & (CONFIG_C_ENV_BOOTBLOCK_SIZE - 1)) != 0) +#error "CONFIG_C_ENV_BOOTBLOCK_SIZE must be a power of 2!" +#endif +#define XIP_ROM_SIZE CONFIG_C_ENV_BOOTBLOCK_SIZE +#else +#define XIP_ROM_SIZE CONFIG_XIP_ROM_SIZE +#endif + .global bootblock_pre_c_entry .code32 @@ -136,13 +145,13 @@ addrsize_set_high: * https://mail.coreboot.org/pipermail/coreboot/2010-October/060922.html */ movl $_program, %eax - andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax + andl $(~(XIP_ROM_SIZE - 1)), %eax orl $MTRR_TYPE_WRPROT, %eax wrmsr movl $MTRR_PHYS_MASK(1), %ecx rdmsr - movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax + movl $(~(XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax wrmsr post_code(0x2e) diff --git a/src/cpu/intel/car/p4-netburst/cache_as_ram.S b/src/cpu/intel/car/p4-netburst/cache_as_ram.S index b7eb37b6a6..2cd0c5e922 100644 --- a/src/cpu/intel/car/p4-netburst/cache_as_ram.S +++ b/src/cpu/intel/car/p4-netburst/cache_as_ram.S @@ -26,6 +26,15 @@ #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE +#if CONFIG(C_ENVIRONMENT_BOOTBLOCK) +#if ((CONFIG_C_ENV_BOOTBLOCK_SIZE & (CONFIG_C_ENV_BOOTBLOCK_SIZE - 1)) != 0) +#error "CONFIG_C_ENV_BOOTBLOCK_SIZE must be a power of 2!" +#endif +#define XIP_ROM_SIZE CONFIG_C_ENV_BOOTBLOCK_SIZE +#else +#define XIP_ROM_SIZE CONFIG_XIP_ROM_SIZE +#endif + .global bootblock_pre_c_entry .code32 @@ -354,13 +363,13 @@ cache_rom: * https://mail.coreboot.org/pipermail/coreboot/2010-October/060922.html */ movl $_program, %eax - andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax + andl $(~(XIP_ROM_SIZE - 1)), %eax orl $MTRR_TYPE_WRPROT, %eax wrmsr movl $MTRR_PHYS_MASK(1), %ecx rdmsr - movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax + movl $(~(XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax wrmsr fill_cache: |