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authorDuncan Laurie <dlaurie@chromium.org>2017-02-01 16:37:29 -0800
committerMartin Roth <martinroth@google.com>2017-02-04 23:05:23 +0100
commit9471d00a4f5acc5697d52e18dd74f909560a9031 (patch)
tree1c659862c0b4d25f1a4f018620d5f326031cfa9c /src
parent561bebfbaa55d5ab0656fbfc4866de88722d9618 (diff)
downloadcoreboot-9471d00a4f5acc5697d52e18dd74f909560a9031.tar.xz
google/eve: Fix DRAM DQS map
This change fixes the two sets of pins that were swapped in the map of DQS signals from CPU to DRAM for channel 1. Although this does not appear to have any impact to the system it does result in different register values for DQS pin mapping that are programmed inside FSP. BUG=chrome-os-partner:58666 TEST=This fix was verified against the current schematic and using FSP debug output. Change-Id: I45b821071ba287493b3b13204b7f5b38e06eee75 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/18279 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/google/eve/romstage.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/google/eve/romstage.c b/src/mainboard/google/eve/romstage.c
index 4ae87fd4bb..2378e9052d 100644
--- a/src/mainboard/google/eve/romstage.c
+++ b/src/mainboard/google/eve/romstage.c
@@ -32,7 +32,7 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
/* DQS CPU<>DRAM map */
const u8 dqs_map[2][8] = {
{ 1, 0, 2, 3, 4, 5, 6, 7 },
- { 1, 0, 4, 5, 3, 2, 7, 6 } };
+ { 1, 0, 5, 4, 2, 3, 7, 6 } };
/* Rcomp resistor */
const u16 rcomp_resistor[] = { 200, 81, 162 };
/* Rcomp target */