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authorJulius Werner <jwerner@chromium.org>2018-08-02 17:42:29 -0700
committerJulius Werner <jwerner@chromium.org>2018-08-07 20:55:58 +0000
commit94e2ec72531c9a0d99081381f3ce3a82a6754af3 (patch)
tree1bfb7d154b9ffd3e00deea224d8f76f87ccc73b8 /src
parentb47b6e9f2808ab3f6c8eb83e363d99e846f498b9 (diff)
downloadcoreboot-94e2ec72531c9a0d99081381f3ce3a82a6754af3.tar.xz
arch: Retire cache_sync_instructions() from <arch/cache.h> (except arm)
cache_sync_instructions() has been superseded by arch_program_segment_loaded() and friends for a while. There are no uses in common code anymore, so let's remove it from <arch/cache.h> for all architectures. arm64 still has an implementation and one reference, but they are not really needed since arch_program_segment_loaded() does the same thing already. Remove them. Leave it in arm(32) since there are several references (including in SoC code) that I don't feel like tracking down and testing right now. Change-Id: I6b776ad49782d981d6f1ef0a0e013812cf408524 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/27879 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src')
-rw-r--r--src/arch/arm64/armv8/cache.c10
-rw-r--r--src/arch/arm64/boot.c2
-rw-r--r--src/arch/arm64/include/armv8/arch/cache.h3
-rw-r--r--src/arch/mips/include/arch/cache.h1
-rw-r--r--src/arch/power8/include/arch/cache.h1
-rw-r--r--src/arch/riscv/include/arch/cache.h1
-rw-r--r--src/arch/x86/include/arch/cache.h7
7 files changed, 0 insertions, 25 deletions
diff --git a/src/arch/arm64/armv8/cache.c b/src/arch/arm64/armv8/cache.c
index 53aefe0bc4..59d56b2902 100644
--- a/src/arch/arm64/armv8/cache.c
+++ b/src/arch/arm64/armv8/cache.c
@@ -118,16 +118,6 @@ void dcache_invalidate_by_mva(void const *addr, size_t len)
dcache_op_va(addr, len, OP_DCIVAC);
}
-void cache_sync_instructions(void)
-{
- uint32_t sctlr = raw_read_sctlr_current();
- if (sctlr & SCTLR_C)
- dcache_clean_all(); /* includes trailing DSB (assembly) */
- else if (sctlr & SCTLR_I)
- dcache_clean_invalidate_all();
- icache_invalidate_all(); /* includdes leading DSB and trailing ISB. */
-}
-
/*
* For each segment of a program loaded this function is called
* to invalidate caches for the addresses of the loaded segment
diff --git a/src/arch/arm64/boot.c b/src/arch/arm64/boot.c
index 3804515392..5fd46a7ebd 100644
--- a/src/arch/arm64/boot.c
+++ b/src/arch/arm64/boot.c
@@ -39,8 +39,6 @@ static void run_payload(struct prog *prog)
else {
uint8_t current_el = get_current_el();
- cache_sync_instructions();
-
printk(BIOS_SPEW, "entry = %p\n", doit);
/* If current EL is not EL3, jump to payload at same EL. */
diff --git a/src/arch/arm64/include/armv8/arch/cache.h b/src/arch/arm64/include/armv8/arch/cache.h
index 8e133efcff..7bf81cf258 100644
--- a/src/arch/arm64/include/armv8/arch/cache.h
+++ b/src/arch/arm64/include/armv8/arch/cache.h
@@ -76,9 +76,6 @@ void dcache_clean_invalidate_all(void);
/* returns number of bytes per cache line */
unsigned int dcache_line_bytes(void);
-/* perform all icache/dcache maintenance needed after loading new code */
-void cache_sync_instructions(void);
-
/* tlb invalidate all */
void tlb_invalidate_all(void);
diff --git a/src/arch/mips/include/arch/cache.h b/src/arch/mips/include/arch/cache.h
index d90a85f3f3..61a3e7c854 100644
--- a/src/arch/mips/include/arch/cache.h
+++ b/src/arch/mips/include/arch/cache.h
@@ -43,7 +43,6 @@ void cache_invalidate_all(uintptr_t start, size_t size);
/* TODO: Global cache API. Implement properly once we finally have a MIPS board
again where we can figure out what exactly these should be doing. */
-static inline void cache_sync_instructions(void) {}
static inline void dcache_clean_all(void) {}
static inline void dcache_invalidate_all(void) {}
static inline void dcache_clean_invalidate_all(void) {}
diff --git a/src/arch/power8/include/arch/cache.h b/src/arch/power8/include/arch/cache.h
index 9b91ac2164..37174475f5 100644
--- a/src/arch/power8/include/arch/cache.h
+++ b/src/arch/power8/include/arch/cache.h
@@ -32,7 +32,6 @@
#define ARCH_CACHE_H
/* TODO: implement these API stubs once caching is available on Power 8 */
-static inline void cache_sync_instructions(void) {}
static inline void dcache_clean_all(void) {}
static inline void dcache_invalidate_all(void) {}
static inline void dcache_clean_invalidate_all(void) {}
diff --git a/src/arch/riscv/include/arch/cache.h b/src/arch/riscv/include/arch/cache.h
index ba7c33da47..37d0662de8 100644
--- a/src/arch/riscv/include/arch/cache.h
+++ b/src/arch/riscv/include/arch/cache.h
@@ -32,7 +32,6 @@
#define ARCH_CACHE_H
/* TODO: implement these API stubs once caching is available on RISC-V */
-static inline void cache_sync_instructions(void) {}
static inline void dcache_clean_all(void) {}
static inline void dcache_invalidate_all(void) {}
static inline void dcache_clean_invalidate_all(void) {}
diff --git a/src/arch/x86/include/arch/cache.h b/src/arch/x86/include/arch/cache.h
index 9f7cda2643..c0d50e650d 100644
--- a/src/arch/x86/include/arch/cache.h
+++ b/src/arch/x86/include/arch/cache.h
@@ -34,13 +34,6 @@
#include <arch/early_variables.h>
#include <cpu/x86/cache.h>
-/*
- * For the purposes of the currently executing CPU loading code that will be
- * run there aren't any cache coherency operations required. This just provides
- * symmetry between architectures.
- */
-static inline void cache_sync_instructions(void) {}
-
/* Executing WBINVD when running out of CAR would not be good, prevent that. */
static inline void dcache_clean_invalidate_all(void)
{