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authorNico Huber <nico.h@gmx.de>2018-05-27 14:01:11 +0200
committerNico Huber <nico.h@gmx.de>2018-05-31 15:11:21 +0000
commit9593e973fa0e3a104837d1df9659b3992d915b34 (patch)
tree8f0aace9603886d215e22c294355a9e5b769133d /src
parent654cc2fe109ea1be4d22447b3d0e6eb22a75b550 (diff)
downloadcoreboot-9593e973fa0e3a104837d1df9659b3992d915b34.tar.xz
soc/{amd,intel}: Use CACHE_ROM_(BASE|SIZE)
Boards could choose a high ROM_SIZE that would result in an MTRR config that conflicts with other resources. Thus, always use the filtered CACHE_ROM_SIZE. Change-Id: I66d36b84ce49c1cb98cb36a4731977baaedf3225 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/26575 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
-rw-r--r--src/soc/amd/stoneyridge/romstage.c2
-rw-r--r--src/soc/intel/apollolake/romstage.c2
-rw-r--r--src/soc/intel/cannonlake/romstage/romstage.c4
-rw-r--r--src/soc/intel/denverton_ns/romstage.c2
-rw-r--r--src/soc/intel/quark/romstage/fsp2_0.c4
-rw-r--r--src/soc/intel/skylake/romstage/romstage_fsp20.c4
6 files changed, 9 insertions, 9 deletions
diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c
index 179168b867..c8efe30fc1 100644
--- a/src/soc/amd/stoneyridge/romstage.c
+++ b/src/soc/amd/stoneyridge/romstage.c
@@ -128,7 +128,7 @@ asmlinkage void car_stage_entry(void)
MTRR_TYPE_WRBACK);
/* Cache the memory-mapped boot media. */
- postcar_frame_add_mtrr(&pcf, -CONFIG_ROM_SIZE, CONFIG_ROM_SIZE,
+ postcar_frame_add_mtrr(&pcf, CACHE_ROM_BASE, CACHE_ROM_SIZE,
MTRR_TYPE_WRPROT);
/*
diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c
index cee23b6d6e..4d6cb27420 100644
--- a/src/soc/intel/apollolake/romstage.c
+++ b/src/soc/intel/apollolake/romstage.c
@@ -234,7 +234,7 @@ asmlinkage void car_stage_entry(void)
/* Cache the memory-mapped boot media. */
if (IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED))
- postcar_frame_add_mtrr(&pcf, -CONFIG_ROM_SIZE, CONFIG_ROM_SIZE,
+ postcar_frame_add_mtrr(&pcf, CACHE_ROM_BASE, CACHE_ROM_SIZE,
MTRR_TYPE_WRPROT);
/*
diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c
index 0459095261..b6cfdbaa8e 100644
--- a/src/soc/intel/cannonlake/romstage/romstage.c
+++ b/src/soc/intel/cannonlake/romstage/romstage.c
@@ -142,8 +142,8 @@ asmlinkage void car_stage_entry(void)
postcar_frame_add_mtrr(&pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK);
/* Cache the ROM as WP just below 4GiB. */
- postcar_frame_add_mtrr(&pcf, 0xFFFFFFFF - CONFIG_ROM_SIZE + 1,
- CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT);
+ postcar_frame_add_mtrr(&pcf, CACHE_ROM_BASE, CACHE_ROM_SIZE,
+ MTRR_TYPE_WRPROT);
run_postcar_phase(&pcf);
}
diff --git a/src/soc/intel/denverton_ns/romstage.c b/src/soc/intel/denverton_ns/romstage.c
index 25d7be0d31..7073627a79 100644
--- a/src/soc/intel/denverton_ns/romstage.c
+++ b/src/soc/intel/denverton_ns/romstage.c
@@ -173,7 +173,7 @@ asmlinkage void car_stage_entry(void)
/* Cache the memory-mapped boot media. */
if (IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED))
- postcar_frame_add_mtrr(&pcf, -CONFIG_ROM_SIZE, CONFIG_ROM_SIZE,
+ postcar_frame_add_mtrr(&pcf, CACHE_ROM_BASE, CACHE_ROM_SIZE,
MTRR_TYPE_WRPROT);
#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)
/*
diff --git a/src/soc/intel/quark/romstage/fsp2_0.c b/src/soc/intel/quark/romstage/fsp2_0.c
index 10e44c1b68..74796448c4 100644
--- a/src/soc/intel/quark/romstage/fsp2_0.c
+++ b/src/soc/intel/quark/romstage/fsp2_0.c
@@ -80,8 +80,8 @@ asmlinkage void *car_stage_c_entry(void)
postcar_frame_add_mtrr(&pcf, 0x80000000, 0x80000, MTRR_TYPE_WRBACK);
/* Cache SPI flash - Write protect not supported */
- postcar_frame_add_mtrr(&pcf, (uint32_t)(-CONFIG_ROM_SIZE),
- CONFIG_ROM_SIZE, MTRR_TYPE_WRTHROUGH);
+ postcar_frame_add_mtrr(&pcf, CACHE_ROM_BASE, CACHE_ROM_SIZE,
+ MTRR_TYPE_WRTHROUGH);
run_postcar_phase(&pcf);
return NULL;
diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c
index 760dcc1e8c..a93407620b 100644
--- a/src/soc/intel/skylake/romstage/romstage_fsp20.c
+++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c
@@ -186,8 +186,8 @@ asmlinkage void car_stage_entry(void)
}
/* Cache the ROM as WP just below 4GiB. */
- postcar_frame_add_mtrr(&pcf, 0xFFFFFFFF - CONFIG_ROM_SIZE + 1,
- CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT);
+ postcar_frame_add_mtrr(&pcf, CACHE_ROM_BASE, CACHE_ROM_SIZE,
+ MTRR_TYPE_WRPROT);
run_postcar_phase(&pcf);
}