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authorGarrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com>2018-03-07 15:38:14 -0600
committerMartin Roth <martinroth@google.com>2018-03-09 17:11:20 +0000
commit9858bd2e3d511ce943207b1e82a9f75853fa637d (patch)
treebe6f1366273021dd99276f14bb336b56f6730b2f /src
parent546923f906308a737d7797cb96f183a121ab4e10 (diff)
downloadcoreboot-9858bd2e3d511ce943207b1e82a9f75853fa637d.tar.xz
soc/amd/stoneyridge: Add ACPI MMIO enable function
In preparation for moving AGESA calls out of bootblock: * Add definitions for needed registers in southbridge.h * Add function to enable AMD FCH ACPI MMIO regions 0xfed80000 to 0xfed81ffff. Will be called by a later commit. BUG=b:65442212 BRANCH=master TEST=abuild, build Gardenia, build boot Grunt (with other changes to call code not committed at this time) Change-Id: If26efa6c6f5b562ba898e7d9da4827833310dc26 Signed-off-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/25025 Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
-rw-r--r--src/soc/amd/stoneyridge/include/soc/southbridge.h3
-rw-r--r--src/soc/amd/stoneyridge/southbridge.c12
2 files changed, 15 insertions, 0 deletions
diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h
index acdaa8a16e..88403e61ad 100644
--- a/src/soc/amd/stoneyridge/include/soc/southbridge.h
+++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h
@@ -32,6 +32,8 @@
#define PSP_MAILBOX_BAR_EN 0x10
/* Power management registers: 0xfed80300 or index/data at IO 0xcd6/cd7 */
+#define PM_ISA_CONTROL 0x04
+#define MMIO_EN BIT(1)
#define PM_PCI_CTRL 0x08
#define FORCE_SLPSTATE_RETRY BIT(25)
#define FORCE_STPCLK_RETRY BIT(24)
@@ -349,6 +351,7 @@ void southbridge_final(void *chip_info);
void southbridge_init(void *chip_info);
void sb_lpc_port80(void);
void sb_lpc_decode(void);
+void sb_acpi_mmio_decode(void);
void sb_pci_port80(void);
void sb_read_mode(u32 mode);
void sb_set_spi100(u16 norm, u16 fast, u16 alt, u16 tpm);
diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c
index 57bd3f08d2..c591c69d64 100644
--- a/src/soc/amd/stoneyridge/southbridge.c
+++ b/src/soc/amd/stoneyridge/southbridge.c
@@ -367,6 +367,18 @@ void sb_lpc_decode(void)
pci_write_config32(SOC_LPC_DEV, LPC_IO_PORT_DECODE_ENABLE, tmp);
}
+void sb_acpi_mmio_decode(void)
+{
+ uint8_t byte;
+
+ /* Enable ACPI MMIO range 0xfed80000 - 0xfed81fff */
+ outb(PM_ISA_CONTROL, PM_INDEX);
+ byte = inb(PM_DATA);
+ byte |= MMIO_EN;
+ outb(PM_ISA_CONTROL, PM_INDEX);
+ outb(byte, PM_DATA);
+}
+
void sb_clk_output_48Mhz(void)
{
u32 ctrl;