diff options
| author | Eric Lai <ericr_lai@compal.corp-partner.google.com> | 2020-02-01 14:25:43 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-02-05 09:56:38 +0000 |
| commit | 9c5263c9c705396113b9553440c1f9250d68bd95 (patch) | |
| tree | fec29b58e614abbb193c281da0b9537e76c180fd /src | |
| parent | a3d79292e7a6adc0c5dc4c53117feb5225bc6225 (diff) | |
| download | coreboot-9c5263c9c705396113b9553440c1f9250d68bd95.tar.xz | |
mb/google/drallion: Fine tune touch screen power sequence
Follow HW change to use GPP_D15 as TS_RST. And change GPP_B21 from pltrst
to deep in order to met power off timing.
BUG=b:143733039
TEST=Check touch screen is functional in s0 and resume from s0ix
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ieec7eb78a05e653f271e348ed11f7e31c08bd5dc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38665
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/google/drallion/variants/drallion/devicetree.cb | 17 | ||||
| -rw-r--r-- | src/mainboard/google/drallion/variants/drallion/gpio.c | 4 |
2 files changed, 17 insertions, 4 deletions
diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb index 97860f4b2d..06d3e5dd26 100644 --- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb +++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb @@ -336,9 +336,15 @@ chip soc/intel/cannonlake register "generic.desc" = ""Wacom Touchscreen"" register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C23_IRQ)" register "generic.probed" = "1" - register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E7)" + register "generic.reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" + register "generic.reset_delay_ms" = "10" + register "generic.reset_off_delay_ms" = "5" + register "generic.stop_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E7)" register "generic.stop_delay_ms" = "20" - register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)" + register "generic.enable_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)" register "generic.enable_delay_ms" = "55" register "generic.has_power_resource" = "1" register "generic.disable_gpio_export_in_crs" = "1" @@ -352,6 +358,10 @@ chip soc/intel/cannonlake register "generic.desc" = ""ELAN Touchscreen"" register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_C23_IRQ)" register "generic.probed" = "1" + register "generic.reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" + register "generic.reset_delay_ms" = "10" + register "generic.reset_off_delay_ms" = "5" register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E7)" register "generic.stop_delay_ms" = "10" @@ -369,6 +379,9 @@ chip soc/intel/cannonlake register "desc" = ""Melfas Touchscreen"" register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_C23_IRQ)" register "probed" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" + register "reset_delay_ms" = "10" + register "reset_off_delay_ms" = "5" register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E7)" register "stop_delay_ms" = "10" register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)" diff --git a/src/mainboard/google/drallion/variants/drallion/gpio.c b/src/mainboard/google/drallion/variants/drallion/gpio.c index f2b70792f7..1c864caff7 100644 --- a/src/mainboard/google/drallion/variants/drallion/gpio.c +++ b/src/mainboard/google/drallion/variants/drallion/gpio.c @@ -78,7 +78,7 @@ static const struct pad_config gpio_table[] = { /* GSPI0_MOSI */ PAD_NC(GPP_B18, NONE), /* GSPI1_CS# */ PAD_NC(GPP_B19, NONE), /* HDD_FALL_INT (nostuff) */ /* GSPI1_CLK */ PAD_NC(GPP_B20, NONE), -/* GSPI1_MISO */ PAD_CFG_GPO(GPP_B21, 0, PLTRST), /* PCH_3.3V_TS_EN */ +/* GSPI1_MISO */ PAD_CFG_GPO(GPP_B21, 0, DEEP), /* PCH_3.3V_TS_EN */ /* GSPI1_MOSI */ PAD_NC(GPP_B22, NONE), /* SML1ALERT# */ PAD_NC(GPP_B23, DN_20K), @@ -124,7 +124,7 @@ static const struct pad_config gpio_table[] = { /* ISH_UART0_RXD */ PAD_CFG_NF(GPP_D13, UP_20K, DEEP, NF1), /* ISH_CPU_UART0_TX */ /* ISH_UART0_TXD */ PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1), -/* ISH_UART0_RTS# */ PAD_NC(GPP_D15, NONE), +/* ISH_UART0_RTS# */ PAD_CFG_GPO(GPP_D15, 0, DEEP), /* TS_RST */ /* ISH_UART0_CTS# */ PAD_CFG_GPI(GPP_D16, NONE, PLTRST), /* DMIC_CLK1 */ PAD_CFG_GPI(GPP_D17, NONE, PLTRST), /* KB_DET# */ /* DMIC_DATA1 */ PAD_CFG_GPI_APIC(GPP_D18, NONE, PLTRST, |