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authorVadim Bendebury <vbendeb@chromium.org>2015-01-09 16:54:19 -0800
committerPatrick Georgi <pgeorgi@google.com>2015-04-17 09:53:39 +0200
commit9dccf1c40bc2543ad12f6a5af9daea8d0ef0ddfa (patch)
treed1748e53dd45497dfda184d3452a0e7fa96d6035 /src
parentf7da3d2a94dc996235b296569d1eff77842fe361 (diff)
downloadcoreboot-9dccf1c40bc2543ad12f6a5af9daea8d0ef0ddfa.tar.xz
uart: pass register width in the coreboot table
Some SOCs (like pistachio, for instance) provide an 8250 compatible UART, which has the same register layout, but mapped to a bus of a different width. Instead of adding a new driver for these controllers, it is better to have coreboot report UART register width to libpayload, and have it adjust the offsets accordingly when accessing the UART. BRANCH=none BUG=chrome-os-partner:31438 TEST=with the rest of the patches integrated depthcharge console messages show up when running on the FPGA board Change-Id: I30b742146069450941164afb04641b967a214d6d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 2c30845f269ec6ae1d53ddc5cda0b4320008fa42 Original-Change-Id: Ia0a37cd5f24a1ee4d0334f8a7e3da5df0069cec4 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/240027 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9738 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src')
-rw-r--r--src/cpu/allwinner/a10/uart_console.c1
-rw-r--r--src/cpu/ti/am335x/uart.c1
-rw-r--r--src/drivers/uart/oxpcie_early.c1
-rw-r--r--src/drivers/uart/pl011.c1
-rw-r--r--src/drivers/uart/uart8250io.c1
-rw-r--r--src/include/boot/coreboot_tables.h1
-rw-r--r--src/lib/coreboot_table.c1
-rw-r--r--src/mainboard/emulation/qemu-riscv/uart.c1
-rw-r--r--src/soc/imgtec/pistachio/uart.c1
-rw-r--r--src/soc/nvidia/tegra124/uart.c1
-rw-r--r--src/soc/nvidia/tegra132/uart.c1
-rw-r--r--src/soc/rockchip/rk3288/uart.c1
-rw-r--r--src/soc/samsung/exynos5250/uart.c1
-rw-r--r--src/soc/samsung/exynos5420/uart.c1
14 files changed, 14 insertions, 0 deletions
diff --git a/src/cpu/allwinner/a10/uart_console.c b/src/cpu/allwinner/a10/uart_console.c
index ff8634856e..35bff79a2f 100644
--- a/src/cpu/allwinner/a10/uart_console.c
+++ b/src/cpu/allwinner/a10/uart_console.c
@@ -34,6 +34,7 @@ void uart_fill_lb(void *data)
serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED;
serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE);
serial.baud = default_baudrate();
+ serial.regwidth = 1;
lb_add_serial(&serial, data);
lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data);
diff --git a/src/cpu/ti/am335x/uart.c b/src/cpu/ti/am335x/uart.c
index 57568341c2..a886e504fa 100644
--- a/src/cpu/ti/am335x/uart.c
+++ b/src/cpu/ti/am335x/uart.c
@@ -195,6 +195,7 @@ void uart_fill_lb(void *data)
serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED;
serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE);
serial.baud = default_baudrate();
+ serial.regwidth = 2;
lb_add_serial(&serial, data);
lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data);
diff --git a/src/drivers/uart/oxpcie_early.c b/src/drivers/uart/oxpcie_early.c
index 343056cdb6..9daafc5fd9 100644
--- a/src/drivers/uart/oxpcie_early.c
+++ b/src/drivers/uart/oxpcie_early.c
@@ -99,6 +99,7 @@ void uart_fill_lb(void *data)
serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED;
serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE);
serial.baud = default_baudrate();
+ serial.regwidth = 1;
lb_add_serial(&serial, data);
lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data);
diff --git a/src/drivers/uart/pl011.c b/src/drivers/uart/pl011.c
index e2db87760a..aa55c682a6 100644
--- a/src/drivers/uart/pl011.c
+++ b/src/drivers/uart/pl011.c
@@ -47,6 +47,7 @@ void uart_fill_lb(void *data)
serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED;
serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE);
serial.baud = default_baudrate();
+ serial.regwidth = 1;
lb_add_serial(&serial, data);
lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data);
diff --git a/src/drivers/uart/uart8250io.c b/src/drivers/uart/uart8250io.c
index 60a8d86361..2cb586e8c2 100644
--- a/src/drivers/uart/uart8250io.c
+++ b/src/drivers/uart/uart8250io.c
@@ -142,6 +142,7 @@ void uart_fill_lb(void *data)
serial.type = LB_SERIAL_TYPE_IO_MAPPED;
serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE);
serial.baud = default_baudrate();
+ serial.regwidth = 1;
lb_add_serial(&serial, data);
lb_add_console(LB_TAG_CONSOLE_SERIAL8250, data);
diff --git a/src/include/boot/coreboot_tables.h b/src/include/boot/coreboot_tables.h
index 74851b2fbb..7b5da64ec3 100644
--- a/src/include/boot/coreboot_tables.h
+++ b/src/include/boot/coreboot_tables.h
@@ -159,6 +159,7 @@ struct lb_serial {
uint32_t type;
uint32_t baseaddr;
uint32_t baud;
+ uint32_t regwidth;
};
#define LB_TAG_CONSOLE 0x0010
diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c
index 6450b5950f..b62f452b10 100644
--- a/src/lib/coreboot_table.c
+++ b/src/lib/coreboot_table.c
@@ -115,6 +115,7 @@ void lb_add_serial(struct lb_serial *new_serial, void *data)
serial->type = new_serial->type;
serial->baseaddr = new_serial->baseaddr;
serial->baud = new_serial->baud;
+ serial->regwidth = new_serial->regwidth;
}
void lb_add_console(uint16_t consoletype, void *data)
diff --git a/src/mainboard/emulation/qemu-riscv/uart.c b/src/mainboard/emulation/qemu-riscv/uart.c
index 6647cde8ea..207f4412b8 100644
--- a/src/mainboard/emulation/qemu-riscv/uart.c
+++ b/src/mainboard/emulation/qemu-riscv/uart.c
@@ -53,6 +53,7 @@ void uart_fill_lb(void *data)
serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED;
serial.baseaddr = 0x3f8;
serial.baud = 115200;
+ serial.regwidth = 1;
lb_add_serial(&serial, data);
lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data);
}
diff --git a/src/soc/imgtec/pistachio/uart.c b/src/soc/imgtec/pistachio/uart.c
index b5892899a5..ff91459d87 100644
--- a/src/soc/imgtec/pistachio/uart.c
+++ b/src/soc/imgtec/pistachio/uart.c
@@ -179,6 +179,7 @@ void uart_fill_lb(void *data)
serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED;
serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE);
serial.baud = default_baudrate();
+ serial.regwidth = 1;
lb_add_serial(&serial, data);
lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data);
diff --git a/src/soc/nvidia/tegra124/uart.c b/src/soc/nvidia/tegra124/uart.c
index 4af00e9906..a25540b025 100644
--- a/src/soc/nvidia/tegra124/uart.c
+++ b/src/soc/nvidia/tegra124/uart.c
@@ -141,6 +141,7 @@ void uart_fill_lb(void *data)
serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED;
serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE);
serial.baud = default_baudrate();
+ serial.regwidth = 1;
lb_add_serial(&serial, data);
lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data);
diff --git a/src/soc/nvidia/tegra132/uart.c b/src/soc/nvidia/tegra132/uart.c
index 17e1a53d22..3a9ac22584 100644
--- a/src/soc/nvidia/tegra132/uart.c
+++ b/src/soc/nvidia/tegra132/uart.c
@@ -154,6 +154,7 @@ void uart_fill_lb(void *data)
serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED;
serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE);
serial.baud = default_baudrate();
+ serial.regwidth = 1;
lb_add_serial(&serial, data);
lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data);
diff --git a/src/soc/rockchip/rk3288/uart.c b/src/soc/rockchip/rk3288/uart.c
index 01759fe573..7685ff9a41 100644
--- a/src/soc/rockchip/rk3288/uart.c
+++ b/src/soc/rockchip/rk3288/uart.c
@@ -160,6 +160,7 @@ void uart_fill_lb(void *data)
serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED;
serial.baseaddr = CONFIG_CONSOLE_SERIAL_UART_ADDRESS;
serial.baud = default_baudrate();
+ serial.regwidth = 1;
lb_add_serial(&serial, data);
lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data);
diff --git a/src/soc/samsung/exynos5250/uart.c b/src/soc/samsung/exynos5250/uart.c
index 997aa0df8d..c23cfed347 100644
--- a/src/soc/samsung/exynos5250/uart.c
+++ b/src/soc/samsung/exynos5250/uart.c
@@ -195,6 +195,7 @@ void uart_fill_lb(void *data)
serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED;
serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE);
serial.baud = default_baudrate();
+ serial.regwidth = 1;
lb_add_serial(&serial, data);
lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data);
diff --git a/src/soc/samsung/exynos5420/uart.c b/src/soc/samsung/exynos5420/uart.c
index e2be882a2e..74e5067b0d 100644
--- a/src/soc/samsung/exynos5420/uart.c
+++ b/src/soc/samsung/exynos5420/uart.c
@@ -186,6 +186,7 @@ void uart_fill_lb(void *data)
serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED;
serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE);
serial.baud = default_baudrate();
+ serial.regwidth = 1;
lb_add_serial(&serial, data);
lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data);