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authorShunqian Zheng <zhengsq@rock-chips.com>2016-04-13 22:30:07 +0800
committerPatrick Georgi <pgeorgi@google.com>2016-05-09 08:42:24 +0200
commita1f873f0695a4ee59184296d72f187810f701196 (patch)
treedc7f0f38d0bba0f7c5b1426eb0de08ecce5a5031 /src
parentfe7aa2096dcc1f83eb27a4a20b4b56f0bccff043 (diff)
downloadcoreboot-a1f873f0695a4ee59184296d72f187810f701196.tar.xz
google/gru: enable uart2 if configured
This patch select gpio pins for UART2 which is the default debug port of rk3399. Please refer to TRM V0.3 Part1 Page 325,395 for GRF details. BRANCH=none BUG=chrome-os-partner:51537 TEST=check logs from console manually Change-Id: I91eeadd543e7e895c3972d8dd7a2195c9d78968b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 0c51955e18d4ff9cd3208697666af4fa77046e0f Original-Change-Id: I960178628f4020a59d100f2f0b2a6be487892549 Original-Signed-off-by: hunag lin <hl@rock-chips.com> Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/338945 Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/14709 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/google/gru/bootblock.c13
1 files changed, 13 insertions, 0 deletions
diff --git a/src/mainboard/google/gru/bootblock.c b/src/mainboard/google/gru/bootblock.c
index bdc75dd589..1a99e8451c 100644
--- a/src/mainboard/google/gru/bootblock.c
+++ b/src/mainboard/google/gru/bootblock.c
@@ -14,10 +14,23 @@
*
*/
+#include <arch/io.h>
#include <bootblock_common.h>
+#include <soc/grf.h>
+#include <console/console.h>
void bootblock_mainboard_early_init(void)
{
+ if (IS_ENABLED(CONFIG_DRIVERS_UART)) {
+ _Static_assert(CONFIG_CONSOLE_SERIAL_UART_ADDRESS == UART2_BASE,
+ "CONSOLE_SERIAL_UART should be UART2");
+
+ /* iomux: select gpio4c[4:3] as uart2 dbg port */
+ write32(&rk3399_grf->iomux_uart2c, IOMUX_UART2C);
+
+ /* grf soc_con7[11:10] use for uart2 select */
+ write32(&rk3399_grf->soc_con7, UART2C_SEL);
+ }
}
void bootblock_mainboard_init(void)