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| author | Wisley Chen <wisley.chen@quanta.corp-partner.google.com> | 2019-08-08 17:31:48 +0800 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2019-08-10 01:35:25 +0000 |
| commit | a23ff7c8ed9fd8ec9a33ca5df41cb62360e02bec (patch) | |
| tree | 094d6a724b6fd6ef3d908e605b7e45b58987ef6d /src | |
| parent | 5cf9ccc57d8de19692603fffe4b932475b22091b (diff) | |
| download | coreboot-a23ff7c8ed9fd8ec9a33ca5df41cb62360e02bec.tar.xz | |
mb/google/octopus: Add G2touch touchscreen support
Add G2touch touchscreen support for Dorp/Vortinija/Vorticon.
BUG=b:139110164
BRANCH=octopus
TEST=emerge-octopus coreboot chromeos-bootimage, and check touchscreen by
evtest.
Change-Id: Ia42757c881ec78b1c676ac984507732717af94a9
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34794
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/google/octopus/variants/meep/overridetree.cb | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/src/mainboard/google/octopus/variants/meep/overridetree.cb b/src/mainboard/google/octopus/variants/meep/overridetree.cb index d7bdd2e936..8881c9d98f 100644 --- a/src/mainboard/google/octopus/variants/meep/overridetree.cb +++ b/src/mainboard/google/octopus/variants/meep/overridetree.cb @@ -219,6 +219,20 @@ chip soc/intel/apollolake register "hid_desc_reg_offset" = "0x20" device i2c 2c on end end + chip drivers/i2c/hid + register "generic.hid" = ""GTCH7503"" + register "generic.desc" = ""G2TOUCH Touchscreen"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPIO_212_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_105)" + register "generic.reset_delay_ms" = "50" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_146)" + register "generic.enable_delay_ms" = "1" + register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 40 on end + end end # - I2C 7 end |