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authorRonald G. Minnich <rminnich@gmail.com>2013-05-31 19:36:52 +0200
committerRonald G. Minnich <rminnich@gmail.com>2013-06-04 22:36:03 +0200
commita296ce75e304dcf163a770e3dc6ca580b7a61d29 (patch)
tree5ad1b4dc9a1f1f7150fb232538ff878e652d4cd4 /src
parent873965e2a7771e9f040b4bbb18bdb9a27ee2bb09 (diff)
downloadcoreboot-a296ce75e304dcf163a770e3dc6ca580b7a61d29.tar.xz
Move the MARK_GRAPHICS_MEM_WRCOMB to x86 architecture
The MARK_GRAPHICS_MEM_WRCOMB was spreading like a cancer since it was defined in sandybridge. It is really more of an x86 thing however, and we now have three systems that can use it. I considered making this more general, since it technically can apply to PTE-based systems like ARM, and maybe we should. But the 'WRCOMB' moniker is usually closely tied to the x86. Change-Id: I3eb6eb2113843643348a5e18e78c53d113899ff8 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/3349 Tested-by: build bot (Jenkins)
Diffstat (limited to 'src')
-rw-r--r--src/arch/x86/Kconfig8
-rw-r--r--src/northbridge/intel/haswell/Kconfig8
-rw-r--r--src/northbridge/intel/sandybridge/Kconfig8
3 files changed, 8 insertions, 16 deletions
diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig
index c7b2434721..69cdc8a5a4 100644
--- a/src/arch/x86/Kconfig
+++ b/src/arch/x86/Kconfig
@@ -1,5 +1,13 @@
menu "Architecture (x86)"
+config MARK_GRAPHICS_MEM_WRCOMB
+ bool "Mark graphics memory as write-combining."
+ default n
+ help
+ The graphics performance may increase if the graphics
+ memory is set as write-combining cache type. This option
+ enables marking the graphics memory as write-combining.
+
# This is an SMP option. It relates to starting up APs.
# It is usually set in mainboard/*/Kconfig.
# TODO: Improve description.
diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig
index 12f865a2e3..f68978040f 100644
--- a/src/northbridge/intel/haswell/Kconfig
+++ b/src/northbridge/intel/haswell/Kconfig
@@ -82,14 +82,6 @@ config DCACHE_RAM_ROMSTAGE_STACK_SIZE
The amount of anticipated stack usage from the data cache
during pre-ram rom stage execution.
-config MARK_GRAPHICS_MEM_WRCOMB
- bool "Mark graphics memory as write-combining."
- default n
- help
- The graphics performance may increase if the graphics
- memory is set as write-combining cache type. This option
- enables marking the graphics memory as write-combining.
-
config HAVE_MRC
bool "Add a System Agent binary"
help
diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig
index 6c9ae99fcd..56d2cd7a38 100644
--- a/src/northbridge/intel/sandybridge/Kconfig
+++ b/src/northbridge/intel/sandybridge/Kconfig
@@ -107,14 +107,6 @@ config DCACHE_RAM_MRC_VAR_SIZE
hex
default 0x4000
-config MARK_GRAPHICS_MEM_WRCOMB
- bool "Mark graphics memory as write-combining."
- default n
- help
- The graphics performance may increase if the graphics
- memory is set as write-combining cache type. This option
- enables marking the graphics memory as write-combining.
-
config HAVE_MRC
bool "Add a System Agent binary"
help