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| author | Gerd Hoffmann <kraxel@redhat.com> | 2013-05-31 09:26:55 +0200 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2013-06-06 20:52:48 +0200 |
| commit | aa588e027301063731b80e3e22a4ea3b1c0c08f1 (patch) | |
| tree | 6ae582d106b4a49c2d0905b39c29675cbcbbf76b /src | |
| parent | cbf30736b60c6076a82ff256b1bd5246a6af83c0 (diff) | |
| download | coreboot-aa588e027301063731b80e3e22a4ea3b1c0c08f1.tar.xz | |
qemu: wind up new cpu chip
Add boot cpu to the device tree. Figure the number of CPUs installed
(using the qemu firmware config interface) and add cpu devices for them,
so they show up in all generated BIOS tables correctly. This gets SMP
going.
Change-Id: I0e99f98942d8ca90150b27fc13c1c7e926a1a644
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-on: http://review.coreboot.org/3345
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/emulation/qemu-x86/Kconfig | 1 | ||||
| -rw-r--r-- | src/mainboard/emulation/qemu-x86/devicetree.cb | 5 | ||||
| -rw-r--r-- | src/mainboard/emulation/qemu-x86/northbridge.c | 46 |
3 files changed, 52 insertions, 0 deletions
diff --git a/src/mainboard/emulation/qemu-x86/Kconfig b/src/mainboard/emulation/qemu-x86/Kconfig index bf21acd5c2..f8167941fd 100644 --- a/src/mainboard/emulation/qemu-x86/Kconfig +++ b/src/mainboard/emulation/qemu-x86/Kconfig @@ -3,6 +3,7 @@ if BOARD_EMULATION_QEMU_X86 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 + select CPU_QEMU_X86 select SOUTHBRIDGE_INTEL_I82371EB select CACHE_AS_RAM select HAVE_OPTION_TABLE diff --git a/src/mainboard/emulation/qemu-x86/devicetree.cb b/src/mainboard/emulation/qemu-x86/devicetree.cb index 11b2a41977..f37454be09 100644 --- a/src/mainboard/emulation/qemu-x86/devicetree.cb +++ b/src/mainboard/emulation/qemu-x86/devicetree.cb @@ -1,4 +1,9 @@ chip mainboard/emulation/qemu-x86 + device cpu_cluster 0 on + chip cpu/qemu-x86 + device lapic 0 on end + end + end device domain 0 on device pci 0.0 on end # northbridge (i440fx) chip southbridge/intel/i82371eb # southbridge diff --git a/src/mainboard/emulation/qemu-x86/northbridge.c b/src/mainboard/emulation/qemu-x86/northbridge.c index d785bebbc4..992a39e673 100644 --- a/src/mainboard/emulation/qemu-x86/northbridge.c +++ b/src/mainboard/emulation/qemu-x86/northbridge.c @@ -1,4 +1,5 @@ #include <console/console.h> +#include <cpu/cpu.h> #include <cpu/x86/lapic_def.h> #include <arch/io.h> #include <arch/ioapic.h> @@ -11,6 +12,8 @@ #include <smbios.h> #include <cbmem.h> +#include "fw_cfg.h" + #include "memory.c" static void cpu_pci_domain_set_resources(device_t dev) @@ -130,6 +133,46 @@ static struct device_operations pci_domain_ops = { #endif }; +static void cpu_bus_init(device_t dev) +{ + initialize_cpus(dev->link_list); +} + +static unsigned int cpu_bus_scan(device_t bus, unsigned int max) +{ + int max_cpus = fw_cfg_max_cpus(); + device_t cpu; + int i; + + if (max_cpus < 0) + return 0; + + /* + * TODO: This only handles the simple "qemu -smp $nr" case + * correctly. qemu also allows to specify the number of + * cores, threads & sockets. + */ + printk(BIOS_INFO, "QEMU: max_cpus is %d\n", max_cpus); + for (i = 0; i < max_cpus; i++) { + cpu = add_cpu_device(bus->link_list, i, 1); + if (cpu) + set_cpu_topology(cpu, 1, 0, i, 0); + } + return max_cpus; +} + +static void cpu_bus_noop(device_t dev) +{ +} + +static struct device_operations cpu_bus_ops = { + .read_resources = cpu_bus_noop, + .set_resources = cpu_bus_noop, + .enable_resources = cpu_bus_noop, + .init = cpu_bus_init, + .scan_bus = cpu_bus_scan, +}; + static void northbridge_enable(struct device *dev) { /* Set the operations if it is a special bus type */ @@ -137,6 +180,9 @@ static void northbridge_enable(struct device *dev) dev->ops = &pci_domain_ops; pci_set_method(dev); } + else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { + dev->ops = &cpu_bus_ops; + } } struct chip_operations mainboard_emulation_qemu_x86_ops = { |