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authorWim Vervoorn <wvervoorn@eltan.com>2019-12-23 16:03:55 +0100
committerNico Huber <nico.h@gmx.de>2020-01-13 11:01:40 +0000
commitaf995bbd756190a7cf4498c26009855806dcdc45 (patch)
tree420ddd02b8983ddf80adcf5134c1848e19f16713 /src
parentdfd89fc85bc61600da6914c6db929296069ae9df (diff)
downloadcoreboot-af995bbd756190a7cf4498c26009855806dcdc45.tar.xz
mb/facebook/monolith: Enable SpeedStep and DPTF
BUG=N/A TEST=tested using fwts on facebook monolith. Change-Id: Ia3dd195f887055448d42a7584e2c88322f0ec44b Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38131 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/facebook/monolith/devicetree.cb8
1 files changed, 6 insertions, 2 deletions
diff --git a/src/mainboard/facebook/monolith/devicetree.cb b/src/mainboard/facebook/monolith/devicetree.cb
index 4a34cabc3d..399d9afc6b 100644
--- a/src/mainboard/facebook/monolith/devicetree.cb
+++ b/src/mainboard/facebook/monolith/devicetree.cb
@@ -20,10 +20,14 @@ chip soc/intel/skylake
# LPC serial IRQ
register "serirq_mode" = "SERIRQ_CONTINUOUS"
- # Enable "Intel Speed Shift Technology"
+ # "Intel SpeedStep Technology"
+ register "eist_enable" = "1"
+
+ # "Intel Speed Shift Technology"
register "speed_shift_enable" = "1"
- register "dptf_enable" = "0"
+ # DPTF
+ register "dptf_enable" = "1"
# FSP Configuration
register "EnableAzalia" = "1"