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authorNathan_chen <Nathan_chen@wistron.corp-partner.google.com>2019-04-30 16:11:35 +0800
committerDuncan Laurie <dlaurie@chromium.org>2019-05-03 16:29:40 +0000
commitb242de5bfc99ef2b63d21a9d1bd9f19bf79ee687 (patch)
tree3b0f06042c4d4948db0d730fe8e334c46f306ece /src
parentaa0929d101ddfb9e64d8febd2bd31ce1037e62ff (diff)
downloadcoreboot-b242de5bfc99ef2b63d21a9d1bd9f19bf79ee687.tar.xz
mb/google/arcada: Add settings for noise mitgation
Enable acoustic noise mitgation for arcada platform, the slow slew rates for Ia and Gt are fast time dived by 8. BUG=b:131144464 TEST=waveform test and hardware validation result pass. Signed-off-by: nathan chen <nathan_chen@wistron.corp-partner.google.com> Change-Id: I395b2fc527705ab207325cfd7147e6af5f300fce Reviewed-on: https://review.coreboot.org/c/coreboot/+/32521 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/google/sarien/variants/arcada/devicetree.cb6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb
index cf64c4bb89..77bd82a64b 100644
--- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb
+++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb
@@ -37,10 +37,10 @@ chip soc/intel/cannonlake
register "tdp_pl2_override" = "51"
register "Device4Enable" = "1"
register "AcousticNoiseMitigation" = "1"
- register "SlowSlewRateForIa" = "0"
- register "SlowSlewRateForGt" = "0"
+ register "SlowSlewRateForIa" = "2"
+ register "SlowSlewRateForGt" = "2"
register "SlowSlewRateForSa" = "0"
- register "SlowSlewRateForFivr" = "0"
+ register "SlowSlewRateForFivr" = "2"
# Enable eDP device
register "DdiPortEdp" = "1"
# Enable HPD for DDI ports B/C