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authorElyes HAOUAS <ehaouas@noos.fr>2019-07-11 09:22:02 +0200
committerMartin Roth <martinroth@google.com>2019-07-15 02:26:52 +0000
commitb56224408ef6ff152ba1544ea6c38cad26576c97 (patch)
treea3c3d7c6a6c7f9322f18726fe40b608c23042494 /src
parent9fe5dde68d8f07a1f78785f48fc39e6acdc98e6b (diff)
downloadcoreboot-b56224408ef6ff152ba1544ea6c38cad26576c97.tar.xz
src: Use '#include <timestamp.h>' when needed
Change-Id: Ic0483982e8115ae99367d08d8ed77b8a316f5405 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34231 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
Diffstat (limited to 'src')
-rw-r--r--src/drivers/intel/fsp1_1/car.c1
-rw-r--r--src/lib/bootblock.c1
-rw-r--r--src/lib/decompressor.c1
-rw-r--r--src/soc/intel/apollolake/bootblock/bootblock.c1
-rw-r--r--src/soc/intel/denverton_ns/bootblock/bootblock.c1
-rw-r--r--src/soc/qualcomm/qcs405/clock.c1
-rw-r--r--src/soc/qualcomm/qcs405/gpio.c1
-rw-r--r--src/soc/qualcomm/qcs405/soc.c1
8 files changed, 2 insertions, 6 deletions
diff --git a/src/drivers/intel/fsp1_1/car.c b/src/drivers/intel/fsp1_1/car.c
index 1e89a8eb89..19eb041eac 100644
--- a/src/drivers/intel/fsp1_1/car.c
+++ b/src/drivers/intel/fsp1_1/car.c
@@ -23,7 +23,6 @@
#include <fsp/util.h>
#include <fsp/memmap.h>
#include <program_loading.h>
-#include <timestamp.h>
/* platform_enter_postcar() determines the stack to use after
* cache-as-ram is torn down as well as the MTRR settings to use,
diff --git a/src/lib/bootblock.c b/src/lib/bootblock.c
index c28a67aceb..3925e90afe 100644
--- a/src/lib/bootblock.c
+++ b/src/lib/bootblock.c
@@ -21,6 +21,7 @@
#include <pc80/mc146818rtc.h>
#include <program_loading.h>
#include <symbols.h>
+#include <timestamp.h>
DECLARE_OPTIONAL_REGION(timestamp);
diff --git a/src/lib/decompressor.c b/src/lib/decompressor.c
index 0529d11390..eb7f16cd88 100644
--- a/src/lib/decompressor.c
+++ b/src/lib/decompressor.c
@@ -19,6 +19,7 @@
#include <delay.h>
#include <program_loading.h>
#include <symbols.h>
+#include <timestamp.h>
extern u8 compressed_bootblock[];
asm (
diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c
index ac6903a9d2..7b4eaef430 100644
--- a/src/soc/intel/apollolake/bootblock/bootblock.c
+++ b/src/soc/intel/apollolake/bootblock/bootblock.c
@@ -35,7 +35,6 @@
#include <soc/pci_devs.h>
#include <soc/pm.h>
#include <spi-generic.h>
-#include <timestamp.h>
static const struct pad_config tpm_spi_configs[] = {
#if CONFIG(SOC_INTEL_GLK)
diff --git a/src/soc/intel/denverton_ns/bootblock/bootblock.c b/src/soc/intel/denverton_ns/bootblock/bootblock.c
index 57e3a2e49b..e9800c8ae5 100644
--- a/src/soc/intel/denverton_ns/bootblock/bootblock.c
+++ b/src/soc/intel/denverton_ns/bootblock/bootblock.c
@@ -22,7 +22,6 @@
#include <soc/bootblock.h>
#include <soc/iomap.h>
#include <spi-generic.h>
-#include <timestamp.h>
#include <console/console.h>
const FSPT_UPD temp_ram_init_params = {
diff --git a/src/soc/qualcomm/qcs405/clock.c b/src/soc/qualcomm/qcs405/clock.c
index 56824a430a..de42147432 100644
--- a/src/soc/qualcomm/qcs405/clock.c
+++ b/src/soc/qualcomm/qcs405/clock.c
@@ -16,7 +16,6 @@
#include <device/mmio.h>
#include <types.h>
#include <delay.h>
-#include <timestamp.h>
#include <commonlib/helpers.h>
#include <string.h>
#include <soc/clock.h>
diff --git a/src/soc/qualcomm/qcs405/gpio.c b/src/soc/qualcomm/qcs405/gpio.c
index 7b2238d77f..fc58fae7ff 100644
--- a/src/soc/qualcomm/qcs405/gpio.c
+++ b/src/soc/qualcomm/qcs405/gpio.c
@@ -16,7 +16,6 @@
#include <device/mmio.h>
#include <types.h>
#include <delay.h>
-#include <timestamp.h>
#include <gpio.h>
void gpio_configure(gpio_t gpio, uint32_t func, uint32_t pull,
diff --git a/src/soc/qualcomm/qcs405/soc.c b/src/soc/qualcomm/qcs405/soc.c
index b3bfb9918a..6735308143 100644
--- a/src/soc/qualcomm/qcs405/soc.c
+++ b/src/soc/qualcomm/qcs405/soc.c
@@ -15,7 +15,6 @@
#include <symbols.h>
#include <device/device.h>
-#include <timestamp.h>
#include <soc/mmu.h>
#include <soc/symbols.h>