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authorKyösti Mälkki <kyosti.malkki@gmail.com>2019-07-04 21:08:17 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2019-07-07 20:03:55 +0000
commitb72b5d95286a2290554399e0803d4ba5e7b87f8d (patch)
tree8ea86f16a8fffce3650e887ccdc0f8dae0947c96 /src
parent3a2660e489d44d29b647e8594e8134e6ee8fc03b (diff)
downloadcoreboot-b72b5d95286a2290554399e0803d4ba5e7b87f8d.tar.xz
arch/x86: Clean up PIRQ_ROUTE
This code is currently only used by via/epia-m850, it is also somewhat buggy. Change-Id: I140e15d584d3f60f7824bcb71ce63724c11e3f46 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34078 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
-rw-r--r--src/Kconfig15
-rw-r--r--src/arch/x86/Kconfig16
-rw-r--r--src/arch/x86/pirq_routing.c12
3 files changed, 21 insertions, 22 deletions
diff --git a/src/Kconfig b/src/Kconfig
index 919d257c62..778f1694b6 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -543,10 +543,6 @@ config HAVE_OPTION_TABLE
file containing NVRAM/CMOS bit definitions.
It defaults to 'n' but can be selected in mainboard/*/Kconfig.
-config PIRQ_ROUTE
- bool
- default n
-
config HAVE_SMI_HANDLER
bool
default n
@@ -591,17 +587,6 @@ config HAVE_PIRQ_TABLE
Whether or not the PIRQ table is actually generated by coreboot
is configurable by the user via GENERATE_PIRQ_TABLE.
-config MAX_PIRQ_LINKS
- int
- default 4
- help
- This variable specifies the number of PIRQ interrupt links which are
- routable. On most chipsets, this is 4, INTA through INTD. Some
- chipsets offer more than four links, commonly up to INTH. They may
- also have a separate link for ATA or IOAPIC interrupts. When the PIRQ
- table specifies links greater than 4, pirq_route_irqs will not
- function properly, unless this variable is correctly set.
-
config COMMON_FADT
bool
default n
diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig
index 06aadedae6..631d981e45 100644
--- a/src/arch/x86/Kconfig
+++ b/src/arch/x86/Kconfig
@@ -329,3 +329,19 @@ config HAVE_CF9_RESET
config HAVE_CF9_RESET_PREPARE
bool
depends on HAVE_CF9_RESET
+
+config PIRQ_ROUTE
+ bool
+ default n
+
+config MAX_PIRQ_LINKS
+ int
+ default 4
+ depends on PIRQ_ROUTE
+ help
+ This variable specifies the number of PIRQ interrupt links which are
+ routable. On most chipsets, this is 4, INTA through INTD. Some
+ chipsets offer more than four links, commonly up to INTH. They may
+ also have a separate link for ATA or IOAPIC interrupts. When the PIRQ
+ table specifies links greater than 4, pirq_route_irqs will not
+ function properly, unless this variable is correctly set.
diff --git a/src/arch/x86/pirq_routing.c b/src/arch/x86/pirq_routing.c
index 15d7411b3f..5f80c9d56c 100644
--- a/src/arch/x86/pirq_routing.c
+++ b/src/arch/x86/pirq_routing.c
@@ -20,10 +20,6 @@
#include <string.h>
#include <device/pci.h>
-void __weak pirq_assign_irqs(const unsigned char pirq[CONFIG_MAX_PIRQ_LINKS])
-{
-}
-
static void check_pirq_routing_table(struct irq_routing_table *rt)
{
uint8_t *addr = (uint8_t *)rt;
@@ -146,8 +142,11 @@ static void pirq_route_irqs(unsigned long addr)
/* Set PCI IRQs. */
for (i = 0; i < num_entries; i++) {
+ u8 bus = pirq_tbl->slots[i].bus;
+ u8 devfn = pirq_tbl->slots[i].devfn;
+
printk(BIOS_DEBUG, "PIRQ Entry %d Dev/Fn: %X Slot: %d\n", i,
- pirq_tbl->slots[i].devfn >> 3, pirq_tbl->slots[i].slot);
+ devfn >> 3, pirq_tbl->slots[i].slot);
for (intx = 0; intx < MAX_INTX_ENTRIES; intx++) {
@@ -178,8 +177,7 @@ static void pirq_route_irqs(unsigned long addr)
}
/* Bus, device, slots IRQs for {A,B,C,D}. */
- pci_assign_irqs(pirq_tbl->slots[i].bus,
- pirq_tbl->slots[i].devfn >> 3, irq_slot);
+ pci_assign_irqs(bus, devfn >> 3, irq_slot);
}
for (i = 0; i < CONFIG_MAX_PIRQ_LINKS; i++)