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authorKyösti Mälkki <kyosti.malkki@gmail.com>2019-12-09 08:08:58 +0200
committerPatrick Georgi <pgeorgi@google.com>2019-12-21 11:37:07 +0000
commitb915faedd503f7904fef9f7ff531262981061473 (patch)
tree03abc99cc2d4f01496556358e1fb7228b567bfbf /src
parent520717dff196e1d1ed61f72a8abadbc114ee6ba1 (diff)
downloadcoreboot-b915faedd503f7904fef9f7ff531262981061473.tar.xz
sb/amd/{agesa,pi}/hudson: Use simple PCI config accessor
Change-Id: I3d8e21e17a0f870d854694e326b10f7d2d04e5ad Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37596 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
-rw-r--r--src/southbridge/amd/agesa/hudson/reset.c4
-rw-r--r--src/southbridge/amd/pi/hudson/reset.c4
2 files changed, 4 insertions, 4 deletions
diff --git a/src/southbridge/amd/agesa/hudson/reset.c b/src/southbridge/amd/agesa/hudson/reset.c
index e3290384dc..ff77eb87d3 100644
--- a/src/southbridge/amd/agesa/hudson/reset.c
+++ b/src/southbridge/amd/agesa/hudson/reset.c
@@ -28,9 +28,9 @@
void cf9_reset_prepare(void)
{
u32 htic;
- htic = pci_io_read_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL);
+ htic = pci_s_read_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL);
htic &= ~HTIC_BIOSR_Detect;
- pci_io_write_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL, htic);
+ pci_s_write_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL, htic);
}
void do_board_reset(void)
diff --git a/src/southbridge/amd/pi/hudson/reset.c b/src/southbridge/amd/pi/hudson/reset.c
index e3290384dc..ff77eb87d3 100644
--- a/src/southbridge/amd/pi/hudson/reset.c
+++ b/src/southbridge/amd/pi/hudson/reset.c
@@ -28,9 +28,9 @@
void cf9_reset_prepare(void)
{
u32 htic;
- htic = pci_io_read_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL);
+ htic = pci_s_read_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL);
htic &= ~HTIC_BIOSR_Detect;
- pci_io_write_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL, htic);
+ pci_s_write_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL, htic);
}
void do_board_reset(void)