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authorRizwan Qureshi <rizwan.qureshi@intel.com>2019-02-17 11:47:06 +0530
committerPatrick Georgi <pgeorgi@google.com>2019-02-27 11:05:26 +0000
commitba482d3972d73a8e899f7a6034c2027778db590f (patch)
tree1190bdb225c70180d01249a249c9e3bfc18c6156 /src
parent8aadab7e96854bf8d43f117724089dc8d5869efd (diff)
downloadcoreboot-ba482d3972d73a8e899f7a6034c2027778db590f.tar.xz
mb/google/hatch: Select SD_PWR_EN Active high config
Hatch implements active high SD_PWR_EN and requires a workaround in _PS0 and _PS3 control methods to make sure SD_PWR_EN stays low in D3. Select MB_HAS_ACTIVE_HIGH_SD_PWR_ENABLE to enable the same. BUG=b:123350329 Change-Id: I96ab9660eb50100207fe9a237f5924b65eae0928 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/c/31446 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/google/hatch/Kconfig1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig
index b97977c648..2290d8c7b8 100644
--- a/src/mainboard/google/hatch/Kconfig
+++ b/src/mainboard/google/hatch/Kconfig
@@ -14,6 +14,7 @@ config BOARD_GOOGLE_BASEBOARD_HATCH
select MAINBOARD_HAS_CHROMEOS
select MAINBOARD_HAS_SPI_TPM_CR50
select MAINBOARD_HAS_TPM2
+ select MB_HAS_ACTIVE_HIGH_SD_PWR_ENABLE
select SOC_INTEL_WHISKEYLAKE
select SYSTEM_TYPE_LAPTOP