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authorGabe Black <gabeblack@google.com>2014-03-26 21:29:45 -0700
committerMarc Jones <marc.jones@se-eng.com>2014-11-14 07:28:02 +0100
commitbab7896e5e04c807bbc3f76d085405c90d247370 (patch)
tree3f5f0181c790641f3d6edb5fafa1f46414a43dec /src
parent14ade701bd6efd396d4caf641e974c564f07c838 (diff)
downloadcoreboot-bab7896e5e04c807bbc3f76d085405c90d247370.tar.xz
tegra124: Add some functions for resetting peripherals.
These make it possible to reset peripherals without having to dig into the crc. BUG=chrome-os-partner:27220 TEST=Built and booted on nyan with EFS and with the TPM bus turned up to 400KHz. BRANCH=None Original-Change-Id: I7e77b719e1ba30d2964cfbfda467f937d80b5b21 Original-Signed-off-by: Gabe Black <gabeblack@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/191810 Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Tested-by: Tom Warren <twarren@nvidia.com> Original-Commit-Queue: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 18c6a48623ae6eff70ca05ea15a7901972a7bba3) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I8f46666bcf51215f332724ea871f14fec2b522f0 Reviewed-on: http://review.coreboot.org/7458 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
Diffstat (limited to 'src')
-rw-r--r--src/soc/nvidia/tegra124/clock.c42
-rw-r--r--src/soc/nvidia/tegra124/include/soc/clock.h8
2 files changed, 50 insertions, 0 deletions
diff --git a/src/soc/nvidia/tegra124/clock.c b/src/soc/nvidia/tegra124/clock.c
index cef4262f99..a81cf5f05a 100644
--- a/src/soc/nvidia/tegra124/clock.c
+++ b/src/soc/nvidia/tegra124/clock.c
@@ -531,3 +531,45 @@ void clock_enable_clear_reset(u32 l, u32 h, u32 u, u32 v, u32 w, u32 x)
if (w) writel(w, &clk_rst->rst_dev_w_clr);
if (x) writel(x, &clk_rst->rst_dev_x_clr);
}
+
+void clock_reset_l(u32 bit)
+{
+ writel(bit, &clk_rst->rst_dev_l_set);
+ udelay(1);
+ writel(bit, &clk_rst->rst_dev_l_clr);
+}
+
+void clock_reset_h(u32 bit)
+{
+ writel(bit, &clk_rst->rst_dev_h_set);
+ udelay(1);
+ writel(bit, &clk_rst->rst_dev_h_clr);
+}
+
+void clock_reset_u(u32 bit)
+{
+ writel(bit, &clk_rst->rst_dev_u_set);
+ udelay(1);
+ writel(bit, &clk_rst->rst_dev_u_clr);
+}
+
+void clock_reset_v(u32 bit)
+{
+ writel(bit, &clk_rst->rst_dev_v_set);
+ udelay(1);
+ writel(bit, &clk_rst->rst_dev_v_clr);
+}
+
+void clock_reset_w(u32 bit)
+{
+ writel(bit, &clk_rst->rst_dev_w_set);
+ udelay(1);
+ writel(bit, &clk_rst->rst_dev_w_clr);
+}
+
+void clock_reset_x(u32 bit)
+{
+ writel(bit, &clk_rst->rst_dev_x_set);
+ udelay(1);
+ writel(bit, &clk_rst->rst_dev_x_clr);
+}
diff --git a/src/soc/nvidia/tegra124/include/soc/clock.h b/src/soc/nvidia/tegra124/include/soc/clock.h
index d4c504642b..ae3e9acfdd 100644
--- a/src/soc/nvidia/tegra124/include/soc/clock.h
+++ b/src/soc/nvidia/tegra124/include/soc/clock.h
@@ -18,6 +18,8 @@
#ifndef __SOC_NVIDIA_TEGRA124_CLOCK_H__
#define __SOC_NVIDIA_TEGRA124_CLOCK_H__
+#include <stdint.h>
+
enum {
CLK_L_CPU = 0x1 << 0,
CLK_L_COP = 0x1 << 1,
@@ -265,6 +267,12 @@ void clock_sdram(u32 m, u32 n, u32 p, u32 setup, u32 ph45, u32 ph90,
void clock_cpu0_config_and_reset(void * entry);
void clock_halt_avp(void);
void clock_enable_clear_reset(u32 l, u32 h, u32 u, u32 v, u32 w, u32 x);
+void clock_reset_l(u32 l);
+void clock_reset_h(u32 h);
+void clock_reset_u(u32 u);
+void clock_reset_v(u32 v);
+void clock_reset_w(u32 w);
+void clock_reset_x(u32 x);
void clock_init(void);
void clock_init_arm_generic_timer(void);
void sor_clock_stop(void);