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authorAntonello Dettori <dev@dettori.io>2016-11-08 18:44:46 +0100
committerMartin Roth <martinroth@google.com>2016-11-15 18:16:38 +0100
commitc63ee26eca18a681478334ea2103984cc8f44d63 (patch)
treed7ef44d18523d1ba1d4ed778858cf24845e616a4 /src
parent9f1f1e0cb81af376ef1ea138939b97332ce61331 (diff)
downloadcoreboot-c63ee26eca18a681478334ea2103984cc8f44d63.tar.xz
mainboard/tyan/s8226: transition away from device_t
Replace the use of the old device_t definition inside mainboard/tyan/s8226. Change-Id: I41729fc03518a7804ae224c773967453a7ab60a7 Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/17309 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/tyan/s8226/BiosCallOuts.c4
-rw-r--r--src/mainboard/tyan/s8226/romstage.c2
2 files changed, 3 insertions, 3 deletions
diff --git a/src/mainboard/tyan/s8226/BiosCallOuts.c b/src/mainboard/tyan/s8226/BiosCallOuts.c
index 0fa9742fc0..fea32cbddd 100644
--- a/src/mainboard/tyan/s8226/BiosCallOuts.c
+++ b/src/mainboard/tyan/s8226/BiosCallOuts.c
@@ -35,7 +35,7 @@
static UINT8 select_socket(UINT8 socket_id)
{
- device_t sm_dev = PCI_DEV(0, 0x14, 0); //SMBUS
+ pci_devfn_t sm_dev = PCI_DEV(0, 0x14, 0); //SMBUS
UINT8 value = 0;
UINT8 gpio52_to_49 = 0;
@@ -67,7 +67,7 @@ static UINT8 select_socket(UINT8 socket_id)
static void restore_socket(UINT8 original_value)
{
- device_t sm_dev = PCI_DEV(0, 0x14, 0); //SMBUS
+ pci_devfn_t sm_dev = PCI_DEV(0, 0x14, 0); //SMBUS
pci_write_config8(sm_dev, PCI_REG_GPIO_52_to_49_CNTRL, original_value);
// TODO: Restore previous GPIO48 configurations?
diff --git a/src/mainboard/tyan/s8226/romstage.c b/src/mainboard/tyan/s8226/romstage.c
index ea877b738f..7460f208ce 100644
--- a/src/mainboard/tyan/s8226/romstage.c
+++ b/src/mainboard/tyan/s8226/romstage.c
@@ -43,7 +43,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x31);
/* For serial port. */
- device_t dev = PCI_DEV(0, 0x14, 3);
+ pci_devfn_t dev = PCI_DEV(0, 0x14, 3);
pci_write_config32(dev, 0x44, 0xff03ffd5);
/* Halt if there was a built in self test failure */