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authorRonald G. Minnich <rminnich@gmail.com>2006-03-14 19:58:14 +0000
committerRonald G. Minnich <rminnich@gmail.com>2006-03-14 19:58:14 +0000
commitc994c973c654817f5e764615776b78b84cd21910 (patch)
tree37e35c7cd905ef9b5cacc8dbd76628c134e5f68c /src
parentd96e098def3ed64be0b775d4a6c058821e33b5ef (diff)
downloadcoreboot-c994c973c654817f5e764615776b78b84cd21910.tar.xz
Fix for nehemiah
other fixes for gx2 ram init. support for sharplfg00l04 -- not working yet. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2197 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/amd/rumba/auto.c18
-rw-r--r--src/mainboard/lippert/frontrunner/auto.c27
-rw-r--r--src/mainboard/via/epia-m/mainboard.c5
-rw-r--r--src/northbridge/amd/gx2/pll_reset.c9
-rw-r--r--src/northbridge/amd/gx2/raminit.c17
-rw-r--r--src/southbridge/amd/cs5535/cs5535_early_setup.c5
6 files changed, 59 insertions, 22 deletions
diff --git a/src/mainboard/amd/rumba/auto.c b/src/mainboard/amd/rumba/auto.c
index 72d1ef4e0e..19f7049c8e 100644
--- a/src/mainboard/amd/rumba/auto.c
+++ b/src/mainboard/amd/rumba/auto.c
@@ -19,6 +19,24 @@
#include "southbridge/amd/cs5535/cs5535_early_smbus.c"
#include "southbridge/amd/cs5535/cs5535_early_setup.c"
#include "northbridge/amd/gx2/raminit.h"
+
+static void sdram_set_spd_registers(const struct mem_controller *ctrl) {
+ msr_t msr;
+ /* 1. Initialize GLMC registers base on SPD values,
+ * Hard coded as XpressROM for now */
+ //print_debug("sdram_enable step 1\r\n");
+ msr = rdmsr(0x20000018);
+ msr.hi = 0x10076013;
+ msr.lo = 0x00003000;
+ wrmsr(0x20000018, msr);
+
+ msr = rdmsr(0x20000019);
+ msr.hi = 0x18000108;
+ msr.lo = 0x696332a3;
+ wrmsr(0x20000019, msr);
+
+
+}
#include "northbridge/amd/gx2/raminit.c"
#include "sdram/generic_sdram.c"
diff --git a/src/mainboard/lippert/frontrunner/auto.c b/src/mainboard/lippert/frontrunner/auto.c
index 72d1ef4e0e..5ad5576291 100644
--- a/src/mainboard/lippert/frontrunner/auto.c
+++ b/src/mainboard/lippert/frontrunner/auto.c
@@ -19,11 +19,32 @@
#include "southbridge/amd/cs5535/cs5535_early_smbus.c"
#include "southbridge/amd/cs5535/cs5535_early_setup.c"
#include "northbridge/amd/gx2/raminit.h"
+
+/* this has to be done on a per-mainboard basis, esp. if you don't have smbus */
+static void sdram_set_spd_registers(const struct mem_controller *ctrl)
+{
+ msr_t msr;
+ /* 1. Initialize GLMC registers base on SPD values,
+ * Hard coded as XpressROM for now */
+ //print_debug("sdram_enable step 1\r\n");
+ msr = rdmsr(0x20000018);
+ msr.hi = 0x10076013;
+ msr.lo = 0x3400;
+ wrmsr(0x20000018, msr);
+
+ msr = rdmsr(0x20000019);
+ msr.hi = 0x18000008;
+ msr.lo = 0x696332a3;
+ wrmsr(0x20000019, msr);
+
+}
+
#include "northbridge/amd/gx2/raminit.c"
#include "sdram/generic_sdram.c"
#include "northbridge/amd/gx2/pll_reset.c"
+
static void msr_init(void)
{
__builtin_wrmsr(0x1808, 0x10f3bf00, 0x22fffc02);
@@ -63,15 +84,15 @@ static void main(unsigned long bist)
console_init();
cs5535_early_setup();
-
+ print_err("done cs5535 early\n");
pll_reset();
-
+ print_err("done pll_reset\n");
/* Halt if there was a built in self test failure */
//report_bist_failure(bist);
sdram_initialize(1, memctrl);
-
+ print_err("Done sdram_initialize\n");
/* Check all of memory */
ram_check(0x00000000, 640*1024);
diff --git a/src/mainboard/via/epia-m/mainboard.c b/src/mainboard/via/epia-m/mainboard.c
index 26e5916f01..da27732d63 100644
--- a/src/mainboard/via/epia-m/mainboard.c
+++ b/src/mainboard/via/epia-m/mainboard.c
@@ -30,6 +30,11 @@ void write_protect_vgabios(void)
device_t dev;
printk_info("write_protect_vgabios\n");
+ /* there are two possible devices. Just do both. */
+ dev = dev_find_device(PCI_VENDOR_ID_VIA, 0x3122, 0);
+ if(dev)
+ pci_write_config8(dev, 0x61, 0xaa);
+
dev = dev_find_device(PCI_VENDOR_ID_VIA, 0x3123, 0);
if(dev)
pci_write_config8(dev, 0x61, 0xaa);
diff --git a/src/northbridge/amd/gx2/pll_reset.c b/src/northbridge/amd/gx2/pll_reset.c
index b84e62e8b2..0e3a3caf95 100644
--- a/src/northbridge/amd/gx2/pll_reset.c
+++ b/src/northbridge/amd/gx2/pll_reset.c
@@ -122,9 +122,14 @@ static void pll_reset(void)
/* get CPU core clock in MHZ */
cpu_core = calibrate_tsc();
- get_memory_speed();
+ print_debug("Cpu core is ");
+ print_debug_hex32(cpu_core);
+ print_debug("\n");
+ //get_memory_speed();
//msr = rdmsr(GLCP_SYS_RSTPLL);
msr = rdmsr(0x4c000014);
+ print_debug("4c000014 is ");
+ print_debug_hex32(msr.hi); print_debug(":"); print_debug_hex32(msr.lo); print_debug("\n");
if (msr.lo & (1 << GLCP_SYS_RSTPLL_BYPASS)) {
print_debug("disable PLL bypass\n\r");
@@ -162,7 +167,7 @@ static void pll_reset(void)
print_debug("\n\r");
//gliu = get_memory_speed();
- get_memory_speed();
+ //get_memory_speed();
//print_debug("Target Memory Clock ");
//print_debug_hex32(gliu);
//print_debug("\n\r");
diff --git a/src/northbridge/amd/gx2/raminit.c b/src/northbridge/amd/gx2/raminit.c
index 95ce72a10e..a2cc474a3a 100644
--- a/src/northbridge/amd/gx2/raminit.c
+++ b/src/northbridge/amd/gx2/raminit.c
@@ -4,10 +4,6 @@ static void sdram_set_registers(const struct mem_controller *ctrl)
{
}
-static void sdram_set_spd_registers(const struct mem_controller *ctrl)
-{
-
-}
/* Section 6.1.3, LX processor databooks, BIOS Initialization Sequence
* Section 4.1.4, GX/CS5535 GeodeROM Porting guide */
@@ -16,19 +12,6 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
int i;
msr_t msr;
- /* 1. Initialize GLMC registers base on SPD values,
- * Hard coded as XpressROM for now */
- //print_debug("sdram_enable step 1\r\n");
- msr = rdmsr(0x20000018);
- msr.hi = 0x10076013;
- msr.lo = 0x00003000;
- wrmsr(0x20000018, msr);
-
- msr = rdmsr(0x20000019);
- msr.hi = 0x18000108;
- msr.lo = 0x696332a3;
- wrmsr(0x20000019, msr);
-
/* 2. clock gating for PMode */
msr = rdmsr(0x20002004);
msr.lo &= ~0x04;
diff --git a/src/southbridge/amd/cs5535/cs5535_early_setup.c b/src/southbridge/amd/cs5535/cs5535_early_setup.c
index ae3b7df441..6c32498aa9 100644
--- a/src/southbridge/amd/cs5535/cs5535_early_setup.c
+++ b/src/southbridge/amd/cs5535/cs5535_early_setup.c
@@ -103,10 +103,15 @@ static int cs5535_early_setup(void)
print_debug("reboot from BIOS reset\n\r");
return;
}
+ print_debug("Setup idsel\r\n");
cs5535_setup_idsel();
+ print_debug("Setup iobase\r\n");
cs5535_setup_iobase();
+ print_debug("Setup gpio\r\n");
cs5535_setup_gpio();
+ print_debug("Setup cis_mode\r\n");
cs5535_setup_cis_mode();
+ print_debug("Setup smbus\r\n");
cs5535_enable_smbus();
//get_memory_speed();
dummy();