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authorNico Huber <nico.huber@secunet.com>2017-05-12 17:10:58 +0200
committerNico Huber <nico.h@gmx.de>2017-05-13 15:33:46 +0200
commitcfd433b96daa2d2f7f4f99fff7608e110b64dca4 (patch)
tree2136415ceb18234dc3a362e2026373508271f04c /src
parentdd2e35edc14b71b81e9600c7e46a5e934f03d51e (diff)
downloadcoreboot-cfd433b96daa2d2f7f4f99fff7608e110b64dca4.tar.xz
nb/intel/x4x: Fix uninitialized variable issue
A left-over from 5e3cb72a71 (nb/x4x: Do not enable IGD when not supported). Should fix coverity issue 1375009. Remove a redundant line that uses the variable `gfxsize` out of its scope and move the variable declaration. Make sure the variable is always initialized, drop unneeded error-handling for `get_option()` and sanitize the read value instead. Change-Id: Iee2beda30d8c74df0f412622c3ff3357819e386b Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/19680 Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src')
-rw-r--r--src/northbridge/intel/x4x/early_init.c13
1 files changed, 5 insertions, 8 deletions
diff --git a/src/northbridge/intel/x4x/early_init.c b/src/northbridge/intel/x4x/early_init.c
index 66bce7234c..c70e3862c1 100644
--- a/src/northbridge/intel/x4x/early_init.c
+++ b/src/northbridge/intel/x4x/early_init.c
@@ -27,7 +27,6 @@
void x4x_early_init(void)
{
- u8 gfxsize;
const pci_devfn_t d0f0 = PCI_DEV(0, 0, 0);
/* Setup MCHBAR. */
@@ -58,19 +57,17 @@ void x4x_early_init(void)
if (!(pci_read_config32(d0f0, D0F0_CAPID0 + 4) & (1 << (46 - 32)))) {
/* Enable internal GFX */
pci_write_config32(d0f0, D0F0_DEVEN, BOARD_DEVEN);
- /* Set preallocated IGD size from cmos */
- if (get_option(&gfxsize, "gfx_uma_size") != CB_SUCCESS) {
- /* 6 for 64MB, default if not set in cmos */
+ /* Set preallocated IGD size from cmos */
+ u8 gfxsize = 6; /* 6 for 64MiB, default if not set in cmos */
+ get_option(&gfxsize, "gfx_uma_size");
+ if (gfxsize > 12)
gfxsize = 6;
- }
- pci_write_config16(d0f0, D0F0_GGC,
- 0x0100 | ((gfxsize + 1) << 4));
+ pci_write_config16(d0f0, D0F0_GGC, 0x0100 | (gfxsize + 1) << 4);
} else { /* Does not feature internal graphics */
pci_write_config32(d0f0, D0F0_DEVEN, D0EN | D1EN | PEG1EN);
pci_write_config16(d0f0, D0F0_GGC, (1 << 1));
}
- pci_write_config16(d0f0, D0F0_GGC, 0x0100 | ((gfxsize + 1) << 4));
}
static void init_egress(void)