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authorGreg Watson <jarrah@users.sourceforge.net>2003-07-20 23:28:01 +0000
committerGreg Watson <jarrah@users.sourceforge.net>2003-07-20 23:28:01 +0000
commitd0580343b6c81697f0050b38ea36ee154d242ac2 (patch)
treeb2c838e68ddf833ddc0b4294a4c98f81daf817e1 /src
parent9b4336cf418d22551bea09d93e1cee79281b110e (diff)
downloadcoreboot-d0580343b6c81697f0050b38ea36ee154d242ac2.tar.xz
chip stuff
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@988 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src')
-rw-r--r--src/config/Config.lb5
-rw-r--r--src/devices/chip.c15
-rw-r--r--src/include/device/chip.h15
-rw-r--r--src/superio/NSC/pc97307/chip.h5
-rw-r--r--src/superio/NSC/pc97307/superio.c31
5 files changed, 51 insertions, 20 deletions
diff --git a/src/config/Config.lb b/src/config/Config.lb
index 9e780027b9..f896cb77a7 100644
--- a/src/config/Config.lb
+++ b/src/config/Config.lb
@@ -71,9 +71,9 @@ makerule linuxbios
end
makerule linuxbios.a
- depends "$(OBJECTS-1)"
+ depends "$(OBJECTS)"
action "rm -f linuxbios.a"
- action "ar cr linuxbios.a $(OBJECTS-1)"
+ action "ar cr linuxbios.a $(OBJECTS)"
end
#makerule crt0.S
@@ -152,6 +152,7 @@ makerule clean
action "rm -f TAGS tags"
action "rm -f docipl"
action "rm -f build_opt_tbl option_table.c crt0.S"
+ action "rm -f chip_*.c"
end
# do standard config files that the user need not specify
diff --git a/src/devices/chip.c b/src/devices/chip.c
new file mode 100644
index 0000000000..d25c92e0d7
--- /dev/null
+++ b/src/devices/chip.c
@@ -0,0 +1,15 @@
+/* chips are arbitrary chips (superio, southbridge, etc.)
+ * They have private structures that define chip resources and default
+ * settings. They have four externally visible functions for control.
+ * They have a generic component which applies to all chips for
+ * path, etc.
+ */
+
+#include <device/chip.h>
+
+void
+chip_configure(struct chip *root, enum chip_pass pass)
+{
+ while (root) {
+ }
+}
diff --git a/src/include/device/chip.h b/src/include/device/chip.h
index ea57ea4b5c..8de91a1129 100644
--- a/src/include/device/chip.h
+++ b/src/include/device/chip.h
@@ -22,6 +22,14 @@ struct lpt_ports {
irq; // irq
};
+enum chip_pass {
+ CHIP_PRE_CONSOLE,
+ CHIP_PRE_DEVICE_ENUMERATE,
+ CHIP_PRE_DEVICE_CONFIGURE,
+ CHIP_PRE_DEVICE_ENABLE,
+ CHIP_PRE_DEVICE_INITIALIZE,
+ CHIP_PRE_BOOT
+};
/* linkages from devices of a type (e.g. superio devices)
@@ -33,10 +41,7 @@ struct chip;
/* there is one of these for each TYPE of chip */
struct chip_control {
- void (*alloc)(struct chip *s);
- void (*pre_pci_init)(struct chip *s);
- void (*init)(struct chip *s);
- void (*finishup)(struct chip *s);
+ void (*enable)(struct chip *, enum chip_pass);
char *path; /* the default path. Can be overridden
* by commands in config
*/
@@ -54,3 +59,5 @@ struct chip {
void *chip_info; /* the dreaded "void *" */
};
+extern struct chip *root;
+extern void chip_configure(struct chip *, enum chip_pass);
diff --git a/src/superio/NSC/pc97307/chip.h b/src/superio/NSC/pc97307/chip.h
new file mode 100644
index 0000000000..d30b7cb26c
--- /dev/null
+++ b/src/superio/NSC/pc97307/chip.h
@@ -0,0 +1,5 @@
+
+struct superio_NSC_pc97307_config {
+ typedef struct com_ports com1;
+ typedef struct lpt_ports lpt;
+};
diff --git a/src/superio/NSC/pc97307/superio.c b/src/superio/NSC/pc97307/superio.c
index 8dc2ca8661..00117d8f32 100644
--- a/src/superio/NSC/pc97307/superio.c
+++ b/src/superio/NSC/pc97307/superio.c
@@ -2,6 +2,7 @@
/* This code is distributed without warranty under the GPL v2 (see COPYING) */
#include <arch/io.h>
+#include <device/chip.h>
#ifndef PNP_INDEX_REG
#define PNP_INDEX_REG 0x15C
@@ -18,26 +19,28 @@
void pnp_output(char address, char data)
{
- outb(address, PNP_INDEX_REG);
- outb(data, PNP_DATA_REG);
+ outb(address, PNP_INDEX_REG);
+ outb(data, PNP_DATA_REG);
}
-void sio_enable(void)
+void sio_enable(struct chip *chip, enum chip_pass pass)
{
- /* Enable Super IO Chip */
- pnp_output(0x07, 6); /* LD 6 = UART1 */
- pnp_output(0x30, 0); /* Dectivate */
- pnp_output(0x60, SIO_COM1_BASE >> 8); /* IO Base */
- pnp_output(0x61, SIO_COM1_BASE & 0xFF); /* IO Base */
- pnp_output(0x30, 1); /* Activate */
+ switch (pass) {
+ case CHIP_PRE_CONSOLE:
+ /* Enable Super IO Chip */
+ pnp_output(0x07, 6); /* LD 6 = UART1 */
+ pnp_output(0x30, 0); /* Dectivate */
+ pnp_output(0x60, chip->control->defaultport >> 8); /* IO Base */
+ pnp_output(0x61, chip->control->defaultport & 0xFF); /* IO Base */
+ pnp_output(0x30, 1); /* Activate */
+ break;
+ default:
+ /* nothing yet */
+ }
}
-#if 0
struct superio_control superio_NSC_pc97307_control = {
- pre_pci_init: (void *)0,
- init: (void *)0,
- finishup: (void *)0,
+ enable: sio_enable,
defaultport: SIO_COM1_BASE,
name: "NSC 87307"
};
-#endif