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authorMartin Roth <martinroth@google.com>2017-07-13 10:27:45 -0700
committerMartin Roth <martinroth@google.com>2017-07-31 14:59:14 +0000
commitd303311ce20c18ce8d7ebb68f937346a099d097a (patch)
tree9e48ae54dbeb8ea57a7d5cc456ec2a4165d87fa1 /src
parent23b93dd7d806e6f8ca899adb0449b5d6accba3ba (diff)
downloadcoreboot-d303311ce20c18ce8d7ebb68f937346a099d097a.tar.xz
sb/intel/fspi89xx: Fix timestamp code
The save_timestamp_to_cmos code was used at Sage before the early cbmem was available. Update it to use the standard timestamp calls, based on the rangeley implementation. Change-Id: I9a3a6609bdc8d03c4b86951daa1cafddd9c1332e Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20564 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src')
-rw-r--r--src/southbridge/intel/fsp_i89xx/romstage.c10
1 files changed, 4 insertions, 6 deletions
diff --git a/src/southbridge/intel/fsp_i89xx/romstage.c b/src/southbridge/intel/fsp_i89xx/romstage.c
index 385e4d6ba3..a08972024f 100644
--- a/src/southbridge/intel/fsp_i89xx/romstage.c
+++ b/src/southbridge/intel/fsp_i89xx/romstage.c
@@ -99,9 +99,9 @@ void main(FSP_INFO_HEADER *fsp_info_header)
post_code(0x40);
-#if IS_ENABLED(CONFIG_COLLECT_TIMESTAMPS)
- save_timestamp_to_cmos(CMOS_MAIN_START_ADDR, rdtsc());
-#endif
+ timestamp_init(get_initial_timestamp());
+ timestamp_add_now(TS_START_ROMSTAGE);
+
pch_enable_lpc();
/* Enable GPIOs */
@@ -151,9 +151,7 @@ void main(FSP_INFO_HEADER *fsp_info_header)
post_code(0x48);
-#if IS_ENABLED(CONFIG_COLLECT_TIMESTAMPS)
- save_timestamp_to_cmos(CMOS_PRE_INITRAM_ADDR, rdtsc());
-#endif
+ timestamp_add_now(TS_BEFORE_INITRAM);
/*
* Call early init to initialize memory and chipset. This function returns