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authorElyes HAOUAS <ehaouas@noos.fr>2018-10-30 07:07:00 +0100
committerPatrick Georgi <pgeorgi@google.com>2018-11-05 09:05:33 +0000
commitd35c7fe1bff55471c62b11d208cf3a71dec30d6d (patch)
treecbae0c724c9632088998e9ff401f212ec960e6b5 /src
parentc4ba0f4cbdd28a8e8339085f56340a5f880014c2 (diff)
downloadcoreboot-d35c7fe1bff55471c62b11d208cf3a71dec30d6d.tar.xz
amd/mtrr: Fix IORR MTRR
IORR MTRR definitions renamed to avoid collision between <cpu/amd/mtrr.h> and <AGESA.h>. Change-Id: I3eeb0c69bbb76039039dc90683670cafcb00ed36 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29352 Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
-rw-r--r--src/cpu/amd/mtrr/amd_mtrr.c2
-rw-r--r--src/include/cpu/amd/mtrr.h18
-rw-r--r--src/northbridge/amd/amdmct/mct/mctdqs_d.c6
-rw-r--r--src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c6
4 files changed, 11 insertions, 21 deletions
diff --git a/src/cpu/amd/mtrr/amd_mtrr.c b/src/cpu/amd/mtrr/amd_mtrr.c
index 8cb6658d18..2002dd8fcb 100644
--- a/src/cpu/amd/mtrr/amd_mtrr.c
+++ b/src/cpu/amd/mtrr/amd_mtrr.c
@@ -138,7 +138,7 @@ void amd_setup_mtrrs(void)
* undefined side effects.
*/
msr.lo = msr.hi = 0;
- for (i = IORR_FIRST; i <= IORR_LAST; i++)
+ for (i = MTRR_IORR0_BASE; i <= MTRR_IORR1_MASK; i++)
wrmsr(i, msr);
/* Enable Variable Mtrrs
diff --git a/src/include/cpu/amd/mtrr.h b/src/include/cpu/amd/mtrr.h
index 46d66f8cef..f6b213e69d 100644
--- a/src/include/cpu/amd/mtrr.h
+++ b/src/include/cpu/amd/mtrr.h
@@ -1,20 +1,10 @@
#ifndef CPU_AMD_MTRR_H
#define CPU_AMD_MTRR_H
-/* FIXME
- * Replace
- * #define IORR_FIRST 0xC0010016
- * #define IORR_LAST 0xC0010019
- * with
- * #define IORR0_BASE 0xC0010016
- * #define IORR0_MASK 0xC0010017
- * #define IORR1_BASE 0xC0010018
- * #define IORR1_MASK 0xC0010019
- * those are also defined in vendorcode <AGESA.h> file.
- */
-
-#define IORR_FIRST 0xC0010016
-#define IORR_LAST 0xC0010019
+#define MTRR_IORR0_BASE 0xC0010016
+#define MTRR_IORR0_MASK 0xC0010017
+#define MTRR_IORR1_BASE 0xC0010018
+#define MTRR_IORR1_MASK 0xC0010019
#define MTRR_READ_MEM (1 << 4)
#define MTRR_WRITE_MEM (1 << 3)
diff --git a/src/northbridge/amd/amdmct/mct/mctdqs_d.c b/src/northbridge/amd/amdmct/mct/mctdqs_d.c
index 5aadcccf56..75fc8a427e 100644
--- a/src/northbridge/amd/amdmct/mct/mctdqs_d.c
+++ b/src/northbridge/amd/amdmct/mct/mctdqs_d.c
@@ -816,10 +816,10 @@ void SetTargetWTIO_D(u32 TestAddr)
u32 lo, hi;
hi = TestAddr >> 24;
lo = TestAddr << 8;
- _WRMSR(IORR_FIRST, lo, hi); /* IORR0 Base */
+ _WRMSR(MTRR_IORR0_BASE, lo, hi); /* IORR0 Base */
hi = 0xFF;
lo = 0xFC000800; /* 64MB Mask */
- _WRMSR(0xC0010017, lo, hi); /* IORR0 Mask */
+ _WRMSR(MTRR_IORR0_MASK, lo, hi); /* IORR0 Mask */
}
@@ -829,7 +829,7 @@ void ResetTargetWTIO_D(void)
hi = 0;
lo = 0;
- _WRMSR(0xc0010017, lo, hi); // IORR0 Mask
+ _WRMSR(MTRR_IORR0_MASK, lo, hi); // IORR0 Mask
}
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
index 8b6a8d41bc..7920e656f5 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
@@ -2148,10 +2148,10 @@ void SetTargetWTIO_D(u32 TestAddr)
u32 lo, hi;
hi = TestAddr >> 24;
lo = TestAddr << 8;
- _WRMSR(IORR_FIRST, lo, hi); /* IORR0 Base */
+ _WRMSR(MTRR_IORR0_BASE, lo, hi); /* IORR0 Base */
hi = 0xFF;
lo = 0xFC000800; /* 64MB Mask */
- _WRMSR(0xC0010017, lo, hi); /* IORR0 Mask */
+ _WRMSR(MTRR_IORR0_MASK, lo, hi); /* IORR0 Mask */
}
void ResetTargetWTIO_D(void)
@@ -2160,7 +2160,7 @@ void ResetTargetWTIO_D(void)
hi = 0;
lo = 0;
- _WRMSR(0xc0010017, lo, hi); /* IORR0 Mask */
+ _WRMSR(MTRR_IORR0_MASK, lo, hi); /* IORR0 Mask */
}
u32 SetUpperFSbase(u32 addr_hi)