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authorKyösti Mälkki <kyosti.malkki@gmail.com>2019-09-30 13:08:44 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2019-10-03 03:12:31 +0000
commitd46bc604137f29905c4cb9f681803c93f77a8aa3 (patch)
treee4cdd3e0468858db8f15efa0a4e07915089e7414 /src
parentce005dac6810e2964e7ff3a7552cad3e1791ae91 (diff)
downloadcoreboot-d46bc604137f29905c4cb9f681803c93f77a8aa3.tar.xz
intel/fsp_baytrail: Drop some PCI scratchpad register definitions
These were unused and somewhat cryptic, assumed purpose was to store pre-CBMEM timestamps in various PCI config space locations. Change-Id: I074294446501d49a9bd3c823a2a794c33f443168 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35731 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
-rw-r--r--src/soc/intel/fsp_baytrail/include/soc/pci_devs.h25
1 files changed, 0 insertions, 25 deletions
diff --git a/src/soc/intel/fsp_baytrail/include/soc/pci_devs.h b/src/soc/intel/fsp_baytrail/include/soc/pci_devs.h
index a6e37dcc96..a920194a8a 100644
--- a/src/soc/intel/fsp_baytrail/include/soc/pci_devs.h
+++ b/src/soc/intel/fsp_baytrail/include/soc/pci_devs.h
@@ -58,18 +58,8 @@
/* SATA */
#define SATA_DEV 0x13
#define SATA_FUNC 0
-# define SATA_MA 0x84
-# define SATA_MAP 0x90
-# define SATA_PSC 0x92
-# define SATA_SP 0xD0
-# define SATA_BIST1 0xE4
-# define SATA_BIST2 0xE8
# define SATA_DEV_FUNC PCI_DEVFN(SATA_DEV,SATA_FUNC)
-#define SATA_MA_BDFO PCI_DEV(BUS0, SATA_DEV, SATA_FUNC), SATA_MA
-#define SATA_SP_BDFO PCI_DEV(BUS0, SATA_DEV, SATA_FUNC), SATA_SP
-#define SATA_BIST1_BDFO PCI_DEV(BUS0, SATA_DEV, SATA_FUNC), SATA_BIST1
-#define SATA_BIST2_BDFO PCI_DEV(BUS0, SATA_DEV, SATA_FUNC), SATA_BIST2
/* xHCI */
#define XHCI_DEV 0x14
@@ -130,12 +120,6 @@
#define HDA_DEV 0x1b
#define HDA_FUNC 0
# define HDA_DEV_FUNC PCI_DEVFN(HDA_DEV,HDA_FUNC)
-# define HDA_AZUBAR 0x14
-# define HDA_MMLA 0x64
-# define HDA_MMUA 0x68
-#define HDA_AZUBAR_BDFO PCI_DEV(BUS0, HDA_DEV, HDA_FUNC), HDA_AZUBAR
-#define HDA_MMLA_BDFO PCI_DEV(BUS0, HDA_DEV, HDA_FUNC), HDA_MMLA
-#define HDA_MMUA_BDFO PCI_DEV(BUS0, HDA_DEV, HDA_FUNC), HDA_MMUA
/* PCIe Ports */
#define PCIE_DEV 0x1c
@@ -189,15 +173,6 @@
# define LPC_BDF PCI_DEV(0, LPC_DEV, LPC_FUNC)
# define SMBUS_DEV_FUNC PCI_DEVFN(SMBUS_DEV,SMBUS_FUNC)
-#define INITIAL_TIMESTAMP_LOCATION HDA_MMUA_BDFO
-#define BEFORE_CAR_TIMESTAMP_LOCATION SATA_BIST1_BDFO
-#define ASM_BEFORE_CAR_TSC_LOC (0x80 << 24 | SATA_DEV_FUNC << 8 | SATA_BIST1)
-#define AFTER_CAR_TIMESTAMP_LOCATION SATA_BIST2_BDFO
-#define ASM_AFTER_CAR_TSC_LOC (0x80 << 24 | SATA_DEV_FUNC << 8 | SATA_BIST2)
-#define START_ROMSTAGE_TIMESTAMP_LOCATION HDA_MMLA_BDFO
-#define BEFORE_RAMINIT_TIMESTAMP_LOCATION SATA_MA_BDFO
-
-
#define SOC_DEVID 0x0f00
#define GFX_DEVID 0x0f31
#define MIPI_DEVID 0x0f38