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authorNaresh G Solanki <naresh.solanki@intel.com>2016-10-24 13:01:28 +0530
committerAaron Durbin <adurbin@chromium.org>2016-10-27 17:01:46 +0200
commitd5353e36483daef462fd37e47aa4c0524f868ace (patch)
tree7618ffa50ae2700fc8ec630b0fab2674f9b7d66d /src
parent6ea1500e48aa86ca0ae5da2227a65a3e5b5420db (diff)
downloadcoreboot-d5353e36483daef462fd37e47aa4c0524f868ace.tar.xz
driver/intel/fsp2_0: Reset on invalid stage cache.
Add config in fsp 2.0/1.1 driver to reset if ramstage stage cache is invalid during S3 resume. Change-Id: I83fe76957c061f20e9afb308e55923806fda4f93 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/17112 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src')
-rw-r--r--src/drivers/intel/fsp1_1/Kconfig4
-rw-r--r--src/drivers/intel/fsp2_0/Kconfig4
-rw-r--r--src/drivers/intel/fsp2_0/stage_cache.c9
3 files changed, 17 insertions, 0 deletions
diff --git a/src/drivers/intel/fsp1_1/Kconfig b/src/drivers/intel/fsp1_1/Kconfig
index 306e09be74..cc3c0a7104 100644
--- a/src/drivers/intel/fsp1_1/Kconfig
+++ b/src/drivers/intel/fsp1_1/Kconfig
@@ -111,4 +111,8 @@ config CHECKLIST_DATA_FILE_LOCATION
string
default "src/vendorcode/intel/fsp/fsp1_1/checklist"
+config RESET_ON_INVALID_RAMSTAGE_CACHE
+ bool "Reset the system on S3 wake when ramstage cache invalid."
+ default n
+
endif #PLATFORM_USES_FSP1_1
diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig
index 3ffb402965..c653148696 100644
--- a/src/drivers/intel/fsp2_0/Kconfig
+++ b/src/drivers/intel/fsp2_0/Kconfig
@@ -90,4 +90,8 @@ config CHECKLIST_DATA_FILE_LOCATION
string
default "src/vendorcode/intel/fsp/fsp2_0/checklist"
+config RESET_ON_INVALID_RAMSTAGE_CACHE
+ bool "Reset the system on S3 wake when ramstage cache invalid."
+ default n
+
endif
diff --git a/src/drivers/intel/fsp2_0/stage_cache.c b/src/drivers/intel/fsp2_0/stage_cache.c
index 2d594e6048..4469a7f3b5 100644
--- a/src/drivers/intel/fsp2_0/stage_cache.c
+++ b/src/drivers/intel/fsp2_0/stage_cache.c
@@ -17,6 +17,8 @@
#include <console/console.h>
#include <fsp/memmap.h>
#include <stage_cache.h>
+#include <reset.h>
+#include <program_loading.h>
void stage_cache_external_region(void **base, size_t *size)
{
@@ -26,3 +28,10 @@ void stage_cache_external_region(void **base, size_t *size)
*size = 0;
}
}
+
+void ramstage_cache_invalid(void)
+{
+ if (IS_ENABLED(CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE))
+ /* Perform cold reset on invalid ramstage cache. */
+ hard_reset();
+}