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| author | Eric Lai <ericr_lai@compal.corp-partner.google.com> | 2019-09-03 16:08:19 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-09-05 14:56:01 +0000 |
| commit | d5c8912f1e49ecae8f95cba9e938cc0931ae86a6 (patch) | |
| tree | 10c2eb7c8d93046308166758af148dc3e6adae4d /src | |
| parent | fdb9805d6884090fd7bf62dbdf9c858692e55fb4 (diff) | |
| download | coreboot-d5c8912f1e49ecae8f95cba9e938cc0931ae86a6.tar.xz | |
soc/intel/cannonlake: memory spd data debug
Add printing SPD data for debug usage.
BUG=b:139397313
BRANCH=N/A
TEST=Tested the on Hatch and checked cbmem log.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I1e257a8ea6ff9c906267841819d2a4b62a9e0b9e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35235
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/cannonlake/cnl_memcfg_init.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/cnl_memcfg_init.c b/src/soc/intel/cannonlake/cnl_memcfg_init.c index d3e5e837fd..6c551ad563 100644 --- a/src/soc/intel/cannonlake/cnl_memcfg_init.c +++ b/src/soc/intel/cannonlake/cnl_memcfg_init.c @@ -81,6 +81,7 @@ static void meminit_spd_data(FSP_M_CONFIG *mem_cfg, uint8_t mem_slot, default: die("nonexistent memory slot"); } + printk(BIOS_INFO, "memory slot: %d configuration done.\n", mem_slot); } /* @@ -112,6 +113,7 @@ static void meminit_cbfs_spd_index(FSP_M_CONFIG *mem_cfg, spd_data_ptr = (uintptr_t)rdev_mmap_full(&spd_rdev); last_spd_index = spd_index; + print_spd_info((unsigned char *)spd_data_ptr); } meminit_spd_data(mem_cfg, mem_slot, spd_data_len, spd_data_ptr); |