diff options
| author | Rizwan Qureshi <rizwan.qureshi@intel.com> | 2016-08-03 12:23:18 +0530 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-08-11 20:49:48 +0200 |
| commit | da723ce42f7e763cae7ac768d13756ad0f06714e (patch) | |
| tree | ea09d1e74d0efff31f382deed98f6855e7504b2d /src | |
| parent | 21c54d26cbac7d1a6ceee2006e88186cc9b5d179 (diff) | |
| download | coreboot-da723ce42f7e763cae7ac768d13756ad0f06714e.tar.xz | |
vendorcode/intel/fsp: Add fsp 2.0 header files for skylake and kabylake
Add FSP 2.0 header files, these files are common for Skylake
and Kabylake, name the folder as skykabylake to signify the same.
Change-Id: I71b43a59c9a9b0adf1ee48285e4a72e24a13df2d
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/16050
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Diffstat (limited to 'src')
4 files changed, 4621 insertions, 0 deletions
diff --git a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/soc/fsp/CpuConfigFspData.h b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/soc/fsp/CpuConfigFspData.h new file mode 100644 index 0000000000..f55d332b4b --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/soc/fsp/CpuConfigFspData.h @@ -0,0 +1,68 @@ +/** @file + FSP CPU Data Config Block. + +@copyright + Copyright (c) 2016 Intel Corporation. All rights reserved + This software and associated documentation (if any) is furnished + under a license and may only be used or copied in accordance + with the terms of the license. Except as permitted by the + license, no part of this software or documentation may be + reproduced, stored in a retrieval system, or transmitted in any + form or by any means without the express written consent of + Intel Corporation. + This file contains an 'Intel Peripheral Driver' and is uniquely + identified as "Intel Reference Module" and is licensed for Intel + CPUs and chipsets under the terms of your license agreement with + Intel or your vendor. This file may be modified by the user, subject + to additional terms of the license agreement. + +@par Specification Reference: +**/ +#ifndef _CPU_CONFIG_FSP_DATA_H_ +#define _CPU_CONFIG_FSP_DATA_H_ +union CPU_CONFIG_FSP_DATA { + struct { + /** + Enable or Disable Advanced Encryption Standard (AES) feature. + For some countries, this should be disabled for legal reasons. + - 0: Disable + - <b>1: Enable</b> + **/ + uint32_t AesEnable : 1; + /** + Processor Early Power On Configuration FCLK setting. + - <b>0: 800 MHz (ULT/ULX)</b>. + - <b>1: 1 GHz (DT/Halo)</b>. Not supported on ULT/ULX. + - 2: 400 MHz. + - 3: Reserved. + **/ + uint32_t FClkFrequency : 2; + uint32_t EnableRsr : 1; ///< Enable or Disable RSR feature; 0: Disable; <b>1: Enable </b> + /** + Policies to obtain CPU temperature. + - <b>0: ACPI thermal management uses EC reported temperature values</b>. + - 1: ACPI thermal management uses DTS SMM mechanism to obtain CPU temperature values. + - 2: ACPI Thermal Management uses EC reported temperature values and DTS SMM is used to handle Out of Spec condition. + **/ + uint32_t EnableDts : 2; + uint32_t SmmbaseSwSmiNumber : 8; ///< Software SMI number for handler to save CPU information in SMRAM. + /** + Enable or Disable Virtual Machine Extensions (VMX) feature. + - 0: Disable + - <b>1: Enable</b> + **/ + uint32_t VmxEnable : 1; + /** + Enable or Disable Trusted Execution Technology (TXT) feature. + - 0: Disable + - <b>1: Enable</b> + **/ + uint32_t TxtEnable : 1; + uint32_t SkipMpInit : 1; ///< For Fsp only, Silicon Initialization will skip MP Initialization (including BSP) if enabled. For non-FSP, this should always be 0. + uint32_t RsvdBits : 15; ///< Reserved for future use + uint64_t MicrocodePatchAddress; ///< Pointer to microcode patch that is suitable for this processor. + } Bits; + uint32_t Uint32[3]; +}; + +#endif // _CPU_CONFIG_FSP_DATA_H_ diff --git a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/soc/fsp/FspUpd.h b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/soc/fsp/FspUpd.h new file mode 100644 index 0000000000..9cb77d0efa --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/soc/fsp/FspUpd.h @@ -0,0 +1,42 @@ +/** @file + +Copyright (c) 2016, Intel Corporation. All rights reserved.<BR> + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + + This file is automatically generated. Please do NOT modify !!! + +**/ + +#ifndef __FSPUPD_H__ +#define __FSPUPD_H__ + +#define FSPT_UPD_SIGNATURE 0x545F4450554C424B /* 'KBLUPD_T' */ + +#define FSPM_UPD_SIGNATURE 0x4D5F4450554C424B /* 'KBLUPD_M' */ + +#define FSPS_UPD_SIGNATURE 0x535F4450554C424B /* 'KBLUPD_S' */ + +#endif diff --git a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/soc/fsp/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/soc/fsp/FspmUpd.h new file mode 100644 index 0000000000..525f85364c --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/soc/fsp/FspmUpd.h @@ -0,0 +1,1587 @@ +/** @file + +Copyright (c) 2016, Intel Corporation. All rights reserved.<BR> + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + + This file is automatically generated. Please do NOT modify !!! + +**/ + +#ifndef __FSPMUPD_H__ +#define __FSPMUPD_H__ + +#include "FspUpd.h" +#include <fsp/upd.h> + + +/// +/// The ChipsetInit Info structure provides the information of ME ChipsetInit CRC and BIOS ChipsetInit CRC. +/// +struct CHIPSET_INIT_INFO { + uint8_t Revision; + uint8_t Rsvd[3]; + uint16_t MeChipInitCrc; + uint16_t BiosChipInitCrc; +} __attribute__((packed)); + + +/** Fsp M Configuration +**/ +struct FSP_M_CONFIG { + +/** Offset 0x0040 - Platform Reserved Memory Size + The minimum platform memory size required to pass control into DXE + 0x400000 : 0x400000 +**/ + uint64_t PlatformMemorySize; + +/** Offset 0x0048 - Memory SPD Pointer Channel 0 Dimm 0 + Pointer to SPD data in Memory +**/ + uint32_t MemorySpdPtr00; + +/** Offset 0x004C - Memory SPD Pointer Channel 0 Dimm 1 + Pointer to SPD data in Memory +**/ + uint32_t MemorySpdPtr01; + +/** Offset 0x0050 - Memory SPD Pointer Channel 1 Dimm 0 + Pointer to SPD data in Memory +**/ + uint32_t MemorySpdPtr10; + +/** Offset 0x0054 - Memory SPD Pointer Channel 1 Dimm 1 + Pointer to SPD data in Memory +**/ + uint32_t MemorySpdPtr11; + +/** Offset 0x0058 - SPD Data Length + Length of SPD Data + 0x100:256 Bytes, 0x200:512 Bytes +**/ + uint16_t MemorySpdDataLen; + +/** Offset 0x005A - Dq Byte Map CH0 + Dq byte mapping between CPU and DRAM, Channel 0: board-dependent +**/ + uint8_t DqByteMapCh0[12]; + +/** Offset 0x0066 - Dq Byte Map CH1 + Dq byte mapping between CPU and DRAM, Channel 1: board-dependent +**/ + uint8_t DqByteMapCh1[12]; + +/** Offset 0x0072 - Dqs Map CPU to DRAM CH 0 + Set Dqs mapping relationship between CPU and DRAM, Channel 0: board-dependent +**/ + uint8_t DqsMapCpu2DramCh0[8]; + +/** Offset 0x007A - Dqs Map CPU to DRAM CH 1 + Set Dqs mapping relationship between CPU and DRAM, Channel 1: board-dependent +**/ + uint8_t DqsMapCpu2DramCh1[8]; + +/** Offset 0x0082 - RcompResister settings + Indicates RcompReister settings: Board-dependent +**/ + uint16_t RcompResistor[3]; + +/** Offset 0x0088 - RcompTarget settings + RcompTarget settings: board-dependent +**/ + uint16_t RcompTarget[5]; + +/** Offset 0x0092 - Dqs Pins Interleaved Setting + Indicates DqPinsInterleaved setting: board-dependent + $EN_DIS +**/ + uint8_t DqPinsInterleaved; + +/** Offset 0x0093 - VREF_CA + CA Vref routing: board-dependent + 0:VREF_CA goes to both CH_A and CH_B, 1: VREF_CA to CH_A and VREF_DQ_A to CH_B, + 2:VREF_CA to CH_A and VREF_DQ_B to CH_B +**/ + uint8_t CaVrefConfig; + +/** Offset 0x0094 - Smram Mask + The SMM Regions AB-SEG and/or H-SEG reserved + 0: Neither, 1:AB-SEG, 2:H-SEG, 3: Both +**/ + uint8_t SmramMask; + +/** Offset 0x0095 - MRC Fast Boot + Enables/Disable the MRC fast path thru the MRC + $EN_DIS +**/ + uint8_t MrcFastBoot; + +/** Offset 0x0096 +**/ + uint16_t UnusedUpdSpace0; + +/** Offset 0x0098 - Intel Enhanced Debug + Intel Enhanced Debug (IED): 0=Disabled, 0x400000=Enabled and 4MB SMRAM occupied + 0 : Disable, 0x400000 : Enable +**/ + uint32_t IedSize; + +/** Offset 0x009C - Tseg Size + Size of SMRAM memory reserved. 0x400000 for Release build and 0x1000000 for Debug build + 0x0400000:4MB, 0x01000000:16MB +**/ + uint32_t TsegSize; + +/** Offset 0x00A0 - MMIO Size + Size of MMIO space reserved for devices. 0(Default)=Auto, non-Zero=size in MB +**/ + uint16_t MmioSize; + +/** Offset 0x00A2 - Probeless Trace + Probeless Trace: 0=Disabled, 1=Enable. Enabling Probeless Trace will reserve 128MB. + This also requires IED to be enabled. + $EN_DIS +**/ + uint8_t ProbelessTrace; + +/** Offset 0x00A3 +**/ + uint16_t UnusedUpdSpace1; + +/** Offset 0x00A5 - Enable SMBus + Enable/disable SMBus controller. + $EN_DIS +**/ + uint8_t SmbusEnable; + +/** Offset 0x00A6 - Enable Trace Hub + Enable/disable Trace Hub function. + $EN_DIS +**/ + uint8_t EnableTraceHub; + +/** Offset 0x00A7 +**/ + uint8_t UnusedUpdSpace2[60]; + +/** Offset 0x00E3 - Internal Graphics Pre-allocated Memory + Size of memory preallocated for internal graphics. + 0x00:0 MB, 0x01:32 MB, 0x02:64 MB +**/ + uint8_t IgdDvmt50PreAlloc; + +/** Offset 0x00E4 - Internal Graphics + Enable/disable internal graphics. + $EN_DIS +**/ + uint8_t InternalGfx; + +/** Offset 0x00E5 - Aperture Size + Select the Aperture Size. + 0:128 MB, 1:256 MB, 2:512 MB +**/ + uint8_t ApertureSize; + +/** Offset 0x00E6 - SA GV + System Agent dynamic frequency support and when enabled memory will be training + at two different frequencies. Only effects ULX/ULT CPUs. 0=Disabled, 1=FixedLow, + 2=FixedHigh, and 3=Enabled. + 0:Disabled, 1:FixedLow, 2:FixedHigh, 3:Enabled +**/ + uint8_t SaGv; + +/** Offset 0x00E7 - Rank Margin Tool + Enable/disable Rank Margin Tool. + $EN_DIS +**/ + uint8_t RMT; + +/** Offset 0x00E8 - DDR Frequency Limit + Maximum Memory Frequency Selections in Mhz. Options are 1067, 1333, 1600, 1867, + 2133, 2400 and 0 for Auto. + 1067:1067, 1333:1333, 1600:1600, 1867:1867, 2133:2133, 2400:2400, 0:Auto +**/ + uint16_t DdrFreqLimit; + +/** Offset 0x00EA - Board Type + MrcBoardType, Options are 0=Mobile/Mobile Halo, 1=Desktop/DT Halo, 5=ULT/ULX/Mobile + Halo, 7=UP Server + 0:Mobile/Mobile Halo, 1:Desktop/DT Halo, 5:ULT/ULX/Mobile Halo, 7:UP Server +**/ + uint8_t UserBd; + +/** Offset 0x00EB +**/ + uint8_t UnusedUpdSpace3[105]; + +/** Offset 0x0154 - MMA Test Content Pointer + Pointer to MMA Test Content in Memory +**/ + uint32_t MmaTestContentPtr; + +/** Offset 0x0158 - MMA Test Content Size + Size of MMA Test Content in Memory +**/ + uint32_t MmaTestContentSize; + +/** Offset 0x015C - MMA Test Config Pointer + Pointer to MMA Test Config in Memory +**/ + uint32_t MmaTestConfigPtr; + +/** Offset 0x0160 - MMA Test Config Size + Size of MMA Test Config in Memory +**/ + uint32_t MmaTestConfigSize; + +/** Offset 0x0164 +**/ + uint8_t UnusedUpdSpace4[19]; + +/** Offset 0x0177 - SPD Profile Selected + Select DIMM timing profile. Options are 0=Default profile, 1=Custom profile, 2=XMP + Profile 1, 3=XMP Profile 2 + 0:Default profile, 1:Custom profile, 2:XMP profile 1, 3:XMP profile 2 +**/ + uint8_t SpdProfileSelected; + +/** Offset 0x0178 - Memory Voltage + Memory Voltage Override (Vddq). Default = no override + 0:Default, 1200:1.20 Volts, 1250:1.25 Volts, 1300:1.30 Volts, 1350:1.35 Volts, 1400:1.40 + Volts, 1450:1.45 Volts, 1500:1.50 Volts, 1550:1.55 Volts, 1600:1.60 Volts, 1650:1.65 Volts +**/ + uint16_t VddVoltage; + +/** Offset 0x017A - Memory Reference Clock + Automatic, 100MHz, 133MHz. + 0:Auto, 1:133MHz, 2:100MHz +**/ + uint8_t RefClk; + +/** Offset 0x017B - Memory Ratio + Automatic or the frequency will equal ratio times reference clock. Set to Auto to + recalculate memory timings listed below. + 0:Auto, 4:4, 5:5, 6:6, 7:7, 8:8, 9:9, 10:10, 11:11, 12:12, 13:13, 14:14, 15:15 +**/ + uint8_t Ratio; + +/** Offset 0x017C - QCLK Odd Ratio + Adds 133 or 100 MHz to QCLK frequency, depending on RefClk + $EN_DIS +**/ + uint8_t OddRatioMode; + +/** Offset 0x017D - tCL + CAS Latency, 0: AUTO, max: 31 +**/ + uint8_t tCL; + +/** Offset 0x017E - tCWL + Min CAS Write Latency Delay Time, 0: AUTO, max: 20 +**/ + uint8_t tCWL; + +/** Offset 0x017F - tFAW + Min Four Activate Window Delay Time, 0: AUTO, max: 63 +**/ + uint16_t tFAW; + +/** Offset 0x0181 - tRAS + RAS Active Time, 0: AUTO, max: 64 +**/ + uint16_t tRAS; + +/** Offset 0x0183 - tRCD/tRP + RAS to CAS delay time and Row Precharge delay time, 0: AUTO, max: 63 +**/ + uint8_t tRCDtRP; + +/** Offset 0x0184 - tREFI + Refresh Interval, 0: AUTO, max: 65535 +**/ + uint16_t tREFI; + +/** Offset 0x0186 - tRFC + Min Refresh Recovery Delay Time, 0: AUTO, max: 1023 +**/ + uint16_t tRFC; + +/** Offset 0x0188 - tRRD + Min Row Active to Row Active Delay Time, 0: AUTO, max: 15 +**/ + uint8_t tRRD; + +/** Offset 0x0189 - tRTP + Min Internal Read to Precharge Command Delay Time, 0: AUTO, max: 15. DDR4 legal + values: 5, 6, 7, 8, 9, 10, 12 +**/ + uint8_t tRTP; + +/** Offset 0x018A - tWR + Min Write Recovery Time, 0: AUTO, legal values: 5, 6, 7, 8, 10, 12, 14, 16, 18, 20, 24 + 0:Auto, 5:5, 6:6, 7:7, 8:8, 10:10, 12:12, 14:14, 16:16, 18:18, 20:20, 24:24 +**/ + uint8_t tWR; + +/** Offset 0x018B - tWTR + Min Internal Write to Read Command Delay Time, 0: AUTO, max: 28 +**/ + uint8_t tWTR; + +/** Offset 0x018C - NMode + System command rate, range 0-2, 0 means auto, 1 = 1N, 2 = 2N +**/ + uint8_t NModeSupport; + +/** Offset 0x018D - DllBwEn[0] + DllBwEn[0], for 1067 (0..7) +**/ + uint8_t DllBwEn0; + +/** Offset 0x018E - DllBwEn[1] + DllBwEn[1], for 1333 (0..7) +**/ + uint8_t DllBwEn1; + +/** Offset 0x018F - DllBwEn[2] + DllBwEn[2], for 1600 (0..7) +**/ + uint8_t DllBwEn2; + +/** Offset 0x0190 - DllBwEn[3] + DllBwEn[3], for 1867 and up (0..7) +**/ + uint8_t DllBwEn3; + +/** Offset 0x0191 +**/ + uint8_t UnusedUpdSpace5[15]; + +/** Offset 0x01A0 - HECI Timeouts + Enable/Disable. 0: Disable, disable timeout check for HECI, 1: enable + $EN_DIS +**/ + uint8_t HeciTimeouts; + +/** Offset 0x01A1 - HECI1 BAR address + BAR address of HECI1 +**/ + uint32_t Heci1BarAddress; + +/** Offset 0x01A5 - HECI2 BAR address + BAR address of HECI2 +**/ + uint32_t Heci2BarAddress; + +/** Offset 0x01A9 - HECI3 BAR address + BAR address of HECI3 +**/ + uint32_t Heci3BarAddress; + +/** Offset 0x01AD +**/ + uint8_t UnusedUpdSpace6[115]; + +/** Offset 0x0220 - SG dGPU Power Delay + SG dGPU delay interval after power enabling: 0=Minimal, 1000=Maximum, default is + 300=300 microseconds +**/ + uint16_t SgDelayAfterPwrEn; + +/** Offset 0x0222 - SG dGPU Reset Delay + SG dGPU delay interval for Reset complete: 0=Minimal, 1000=Maximum, default is 100=100 + microseconds +**/ + uint16_t SgDelayAfterHoldReset; + +/** Offset 0x0224 - MMIO size adjustment for AUTO mode + Positive number means increasing MMIO size, Negative value means decreasing MMIO + size: 0 (Default)=no change to AUTO mode MMIO size +**/ + uint16_t MmioSizeAdjustment; + +/** Offset 0x0226 - Enable/Disable DMI GEN3 Static EQ Phase1 programming + Program DMI Gen3 EQ Phase1 Static Presets. Disabled(0x0): Disable EQ Phase1 Static + Presets Programming, Enabled(0x1)(Default): Enable EQ Phase1 Static Presets Programming + $EN_DIS +**/ + uint8_t DmiGen3ProgramStaticEq; + +/** Offset 0x0227 - Enable/Disable PEG 0 + Disabled(0x0): Disable PEG Port, Enabled(0x1): Enable PEG Port (If Silicon SKU permits + it), Auto(0x2)(Default): If an endpoint is present, enable the PEG Port, Disable otherwise + 0:Disable, 1:Enable, 2:AUTO +**/ + uint8_t Peg0Enable; + +/** Offset 0x0228 - Enable/Disable PEG 1 + Disabled(0x0): Disable PEG Port, Enabled(0x1): Enable PEG Port (If Silicon SKU permits + it), Auto(0x2)(Default): If an endpoint is present, enable the PEG Port, Disable otherwise + 0:Disable, 1:Enable, 2:AUTO +**/ + uint8_t Peg1Enable; + +/** Offset 0x0229 - Enable/Disable PEG 2 + Disabled(0x0): Disable PEG Port, Enabled(0x1): Enable PEG Port (If Silicon SKU permits + it), Auto(0x2)(Default): If an endpoint is present, enable the PEG Port, Disable otherwise + 0:Disable, 1:Enable, 2:AUTO +**/ + uint8_t Peg2Enable; + +/** Offset 0x022A - PEG 0 Max Link Speed + Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1 + Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed + 0:Auto, 1:Gen1, 2:Gen2, 3:Gen3 +**/ + uint8_t Peg0MaxLinkSpeed; + +/** Offset 0x022B - PEG 1 Max Link Speed + Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1 + Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed + 0:Auto, 1:Gen1, 2:Gen2, 3:Gen3 +**/ + uint8_t Peg1MaxLinkSpeed; + +/** Offset 0x022C - PEG 2 Max Link Speed + Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1 + Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed + 0:Auto, 1:Gen1, 2:Gen2, 3:Gen3 +**/ + uint8_t Peg2MaxLinkSpeed; + +/** Offset 0x022D - PEG 0 Max Link Width + Auto (Default)(0x0): Maximum possible link width, (0x1): Limit Link to x1, (0x2): + Limit Link to x2, (0x3):Limit Link to x4, (0x4): Limit Link to x8 + 0:Auto, 1:x1, 2:x2, 3:x4, 4:x8 +**/ + uint8_t Peg0MaxLinkWidth; + +/** Offset 0x022E - PEG 1 Max Link Width + Auto (Default)(0x0): Maximum possible link width, (0x1): Limit Link to x1, (0x2): + Limit Link to x2, (0x3):Limit Link to x4 + 0:Auto, 1:x1, 2:x2, 3:x4 +**/ + uint8_t Peg1MaxLinkWidth; + +/** Offset 0x022F - PEG 2 Max Link Width + Auto (Default)(0x0): Maximum possible link width, (0x1): Limit Link to x1, (0x2): + Limit Link to x2 + 0:Auto, 1:x1, 2:x2 +**/ + uint8_t Peg2MaxLinkWidth; + +/** Offset 0x0230 - Power down unused lanes on PEG 0 + (0x0): Do not power down any lane, (0x1): Bios will power down unused lanes based + on the max possible link width + 0:No power saving, 1:Auto +**/ + uint8_t Peg0PowerDownUnusedLanes; + +/** Offset 0x0231 - Power down unused lanes on PEG 1 + (0x0): Do not power down any lane, (0x1): Bios will power down unused lanes based + on the max possible link width + 0:No power saving, 1:Auto +**/ + uint8_t Peg1PowerDownUnusedLanes; + +/** Offset 0x0232 - Power down unused lanes on PEG 2 + (0x0): Do not power down any lane, (0x1): Bios will power down unused lanes based + on the max possible link width + 0:No power saving, 1:Auto +**/ + uint8_t Peg2PowerDownUnusedLanes; + +/** Offset 0x0233 - PCIe ASPM programming will happen in relation to the Oprom + Select when PCIe ASPM programming will happen in relation to the Oprom. Before(0x0)(Default): + Do PCIe ASPM programming before Oprom, After(0x1): Do PCIe ASPM programming after + Oprom, requires an SMI handler to save/restore ASPM settings during S3 resume + 0:Before, 1:After +**/ + uint8_t InitPcieAspmAfterOprom; + +/** Offset 0x0234 - PCIe Disable Spread Spectrum Clocking + PCIe Disable Spread Spectrum Clocking. Normal Operation(0x0)(Default) - SSC enabled, + Disable SSC(0X1) - Disable SSC per platform design or for compliance testing + 0:Normal Operation, 1:Disable SSC +**/ + uint8_t PegDisableSpreadSpectrumClocking; + +/** Offset 0x0235 - DMI Gen3 Root port preset values per lane + Used for programming DMI Gen3 preset values per lane. Range: 0-9, 8 is default for each lane +**/ + uint8_t DmiGen3RootPortPreset[4]; + +/** Offset 0x0239 - DMI Gen3 End port preset values per lane + Used for programming DMI Gen3 preset values per lane. Range: 0-9, 7 is default for each lane +**/ + uint8_t DmiGen3EndPointPreset[4]; + +/** Offset 0x023D - DMI Gen3 End port Hint values per lane + Used for programming DMI Gen3 Hint values per lane. Range: 0-6, 2 is default for each lane +**/ + uint8_t DmiGen3EndPointHint[4]; + +/** Offset 0x0241 - DMI Gen3 RxCTLEp per-Bundle control + Range: 0-15, 12 is default for each bundle, must be specified based upon platform design +**/ + uint8_t DmiGen3RxCtlePeaking[2]; + +/** Offset 0x0243 - PEG Gen3 RxCTLEp per-Bundle control + Range: 0-15, 12 is default for each bundle, must be specified based upon platform design +**/ + uint8_t PegGen3RxCtlePeaking[8]; + +/** Offset 0x024B - Memory data pointer for saved preset search results + The reference code will store the Gen3 Preset Search results in the SaDataHob's + PegData structure (SA_PEG_DATA) and platform code can save/restore this data to + skip preset search in the following boots. Range: 0-0xFFFFFFFF, default is 0 +**/ + uint32_t PegDataPtr; + +/** Offset 0x024F - PEG PERST# GPIO information + The reference code will use the information in this structure in order to reset + PCIe Gen3 devices during equalization, if necessary +**/ + uint8_t PegGpioData[16]; + +/** Offset 0x025F +**/ + uint8_t UnusedUpdSpace7; + +/** Offset 0x0260 - DeEmphasis control for DMI + DeEmphasis control for DMI. 0=-6dB, 1(Default)=-3.5 dB + 0: -6dB, 1: -3.5dB +**/ + uint8_t DmiDeEmphasis; + +/** Offset 0x0261 - PCIe Hot Plug Enable/Disable per port + 0(Default): Disable, 1: Enable +**/ + uint8_t PegRootPortHPE[3]; + +/** Offset 0x0264 - Selection of the primary display device + 0=iGFX, 1=PEG, 2=PCIe Graphics on PCH, 3(Default)=AUTO, 4=Switchable Graphics + 0:iGFX, 1:PEG, 2:PCIe Graphics on PCH, 3:AUTO, 4:Switchable Graphics +**/ + uint8_t PrimaryDisplay; + +/** Offset 0x0265 - Temporary MMIO address for GTTMMADR + The reference code will use the information in this structure in order to reset + PCIe Gen3 devices during equalization, if necessary +**/ + uint32_t GttMmAdr; + +/** Offset 0x0269 - Selection of iGFX GTT Memory size + 1=2MB, 2=4MB, 3=8MB, Default is 3 + 1:2MB, 2:4MB, 3:8MB +**/ + uint16_t GttSize; + +/** Offset 0x026B - Switchable Graphics GPIO information for PEG 0 + Switchable Graphics GPIO information for PEG 0, for Reset, power and wake GPIOs +**/ + uint8_t SaRtd3Pcie0Gpio[24]; + +/** Offset 0x0283 - Switchable Graphics GPIO information for PEG 1 + Switchable Graphics GPIO information for PEG 1, for Reset, power and wake GPIOs +**/ + uint8_t SaRtd3Pcie1Gpio[24]; + +/** Offset 0x029B - Switchable Graphics GPIO information for PEG 2 + Switchable Graphics GPIO information for PEG 2, for Reset, power and wake GPIOs +**/ + uint8_t SaRtd3Pcie2Gpio[24]; + +/** Offset 0x02B3 - PEG root port Device number for Switchable Graphics dGPU + Device number to indicate which PEG root port has dGPU +**/ + uint8_t RootPortDev; + +/** Offset 0x02B4 - PEG root port Function number for Switchable Graphics dGPU + Function number to indicate which PEG root port has dGPU +**/ + uint8_t RootPortFun; + +/** Offset 0x02B5 - Enable/Disable MRC TXT dependency + When enabled MRC execution will wait for TXT initialization to be done first. Disabled(0x0)(Default): + MRC will not wait for TXT initialization, Enabled(0x1): MRC will wait for TXT initialization + $EN_DIS +**/ + uint8_t TxtImplemented; + +/** Offset 0x02B6 - Enable/Disable SA OcSupport + Enable: Enable SA OcSupport, Disable(Default): Disable SA OcSupport + $EN_DIS +**/ + uint8_t SaOcSupport; + +/** Offset 0x02B7 - GT slice Voltage Mode + 0(Default): Adaptive, 1: Override + 0: Adaptive, 1: Override +**/ + uint8_t GtsVoltageMode; + +/** Offset 0x02B8 - GT unslice Voltage Mode + 0(Default): Adaptive, 1: Override + 0: Adaptive, 1: Override +**/ + uint8_t GtusVoltageMode; + +/** Offset 0x02B9 - Maximum GTs turbo ratio override + 0(Default)=Minimal/Auto, 60=Maximum +**/ + uint8_t GtsMaxOcRatio; + +/** Offset 0x02BA - The voltage offset applied to GT slice + 0(Default)=Minimal, 1000=Maximum +**/ + uint16_t GtsVoltageOffset; + +/** Offset 0x02BC - The GT slice voltage override which is applied to the entire range of GT frequencies + 0(Default)=Minimal, 2000=Maximum +**/ + uint16_t GtsVoltageOverride; + +/** Offset 0x02BE - adaptive voltage applied during turbo frequencies + 0(Default)=Minimal, 2000=Maximum +**/ + uint16_t GtsExtraTurboVoltage; + +/** Offset 0x02C0 - voltage offset applied to GT unslice + 0(Default)=Minimal, 2000=Maximum +**/ + uint16_t GtusVoltageOffset; + +/** Offset 0x02C2 - GT unslice voltage override which is applied to the entire range of GT frequencies + 0(Default)=Minimal, 2000=Maximum +**/ + uint16_t GtusVoltageOverride; + +/** Offset 0x02C4 - adaptive voltage applied during turbo frequencies + 0(Default)=Minimal, 2000=Maximum +**/ + uint16_t GtusExtraTurboVoltage; + +/** Offset 0x02C6 - voltage offset applied to the SA + 0(Default)=Minimal, 1000=Maximum +**/ + uint16_t SaVoltageOffset; + +/** Offset 0x02C8 - EDRAM ratio override + EdramRatio is deprecated on Kabylake +**/ + uint8_t EdramRatio; + +/** Offset 0x02C9 - Maximum GTus turbo ratio override + 0(Default)=Minimal, 60=Maximum +**/ + uint8_t GtusMaxOcRatio; + +/** Offset 0x02CA - BIST on Reset + Enable or Disable BIST on Reset; <b>0: Disable</b>; 1: Enable. + $EN_DIS +**/ + uint8_t BistOnReset; + +/** Offset 0x02CB - Skip Stop PBET Timer Enable/Disable + Skip Stop PBET Timer; <b>0: Disable</b>; 1: Enable + $EN_DIS +**/ + uint8_t SkipStopPbet; + +/** Offset 0x02CC - C6DRAM power gating feature + This policy indicates whether or not BIOS should allocate PRMRR memory for C6DRAM + power gating feature.- 0: Don't allocate any PRMRR memory for C6DRAM power gating + feature.- <b>1: Allocate PRMRR memory for C6DRAM power gating feature</b>. + $EN_DIS +**/ + uint8_t EnableC6Dram; + +/** Offset 0x02CD - Over clocking support + Over clocking support; <b>0: Disable</b>; 1: Enable + $EN_DIS +**/ + uint8_t OcSupport; + +/** Offset 0x02CE - Over clocking Lock + Over clocking Lock Enable/Disable; <b>0: Disable</b>; 1: Enable. + $EN_DIS +**/ + uint8_t OcLock; + +/** Offset 0x02CF - Maximum Core Turbo Ratio Override + Maximum core turbo ratio override allows to increase CPU core frequency beyond the + fused max turbo ratio limit. <b>0: Hardware defaults.</b> Range: 0-83 + 0 : 83 +**/ + uint8_t CoreMaxOcRatio; + +/** Offset 0x02D0 - Core voltage mode + Core voltage mode; <b>0: Adaptive</b>; 1: Override. + $EN_DIS +**/ + uint8_t CoreVoltageMode; + +/** Offset 0x02D1 - Minimum clr turbo ratio override + Minimum clr turbo ratio override. <b>0: Hardware defaults.</b> Range: 0-83 + 0x0:0xFF +**/ + uint8_t RingMinOcRatio; + +/** Offset 0x02D2 - Maximum clr turbo ratio override + Maximum clr turbo ratio override allows to increase CPU clr frequency beyond the + fused max turbo ratio limit. <b>0: Hardware defaults.</b> Range: 0-83 + 0x0:0xFF +**/ + uint8_t RingMaxOcRatio; + +/** Offset 0x02D3 - Hyper Threading Enable/Disable + Enable or Disable Hyper Threading; 0: Disable; <b>1: Enable</b> + $EN_DIS +**/ + uint8_t HyperThreading; + +/** Offset 0x02D4 - Enable or Disable CPU Ratio Override + Enable or Disable CPU Ratio Override; <b>0: Disable</b>; 1: Enable. + $EN_DIS +**/ + uint8_t CpuRatioOverride; + +/** Offset 0x02D5 - CPU ratio value + CPU ratio value. Valid Range 0 to 63 + 0x0:0xFF +**/ + uint8_t CpuRatio; + +/** Offset 0x02D6 - Boot frequency + Sets the boot frequency starting from reset vector.- 0: Maximum battery performance.- + <b>1: Maximum non-turbo performance</b>.- 2: Turbo performance. @note If Turbo + is selected BIOS will start in max non-turbo mode and switch to Turbo mode. + 0x0:0xFF +**/ + uint8_t BootFrequency; + +/** Offset 0x02D7 - Number of active cores + Number of active cores(Depends on Number of cores). <b>0: All</b>;<b>1: 1 </b>;<b>2: + 2 </b>;<b>3: 3 </b> + 0x0:0xFF +**/ + uint8_t ActiveCoreCount; + +/** Offset 0x02D8 - Processor Early Power On Configuration FCLK setting + <b>0: 800 MHz (ULT/ULX)</b>. <b>1: 1 GHz (DT/Halo)</b>. Not supported on ULT/ULX.- + 2: 400 MHz. - 3: Reserved + 0x0:0xFF +**/ + uint8_t FClkFrequency; + +/** Offset 0x02D9 - Power JTAG in C10 and deeper power states + Power JTAG in C10 and deeper power states; <b>0: Disable</b>; 1: Enable. + $EN_DIS +**/ + uint8_t JtagC10PowerGateDisable; + +/** Offset 0x02DA - Enable or Disable VMX + Enable or Disable VMX; 0: Disable; <b>1: Enable</b>. + $EN_DIS +**/ + uint8_t VmxEnable; + +/** Offset 0x02DB - AVX2 Ratio Offset + 0(Default)= No Offset. Range 0 - 31. Specifies number of bins to decrease AVX ratio + vs. Core Ratio. Uses Mailbox MSR 0x150, cmd 0x1B. +**/ + uint8_t Avx2RatioOffset; + +/** Offset 0x02DC - BCLK Adaptive Voltage Enable + When enabled, the CPU V/F curves are aware of BCLK frequency when calculated. </b>0: + Disable;<b> 1: Enable + $EN_DIS +**/ + uint8_t BclkAdaptiveVoltage; + +/** Offset 0x02DD - core voltage override + The core voltage override which is applied to the entire range of cpu core frequencies. + Valid Range 0 to 2000 + 0x0:0xFFFF +**/ + uint16_t CoreVoltageOverride; + +/** Offset 0x02DF - Core Turbo voltage Adaptive + Extra Turbo voltage applied to the cpu core when the cpu is operating in turbo mode. + Valid Range 0 to 2000 + 0x0:0xFFFF +**/ + uint16_t CoreVoltageAdaptive; + +/** Offset 0x02E1 - Core Turbo voltage Offset + The voltage offset applied to the core while operating in turbo mode.Valid Range 0 to 1000 + 0x0:0xFFFF +**/ + uint16_t CoreVoltageOffset; + +/** Offset 0x02E3 - Core PLL voltage offset + Core PLL voltage offset. <b>0: No offset</b>. Range 0-63 + 0x0:0xFFFF +**/ + uint16_t CorePllVoltageOffset; + +/** Offset 0x02E5 - BiosGuard + Enable/Disable. 0: Disable, Enable/Disable BIOS Guard feature, 1: enable + $EN_DIS +**/ + uint8_t BiosGuard; + +/** Offset 0x02E6 - EnableSgx + Enable/Disable. 0: Disable, Enable/Disable SGX feature, 1: enable + $EN_DIS +**/ + uint8_t EnableSgx; + +/** Offset 0x02E7 - Txt + Enable/Disable. 0: Disable, Enable/Disable Txt feature, 1: enable + $EN_DIS +**/ + uint8_t Txt; + +/** Offset 0x02E8 - FlashWearOutProtection + Enable/Disable. 0: Disable, Enable/Disable FlashWearOutProtection feature, 1: enable + $EN_DIS +**/ + uint8_t FlashWearOutProtection; + +/** Offset 0x02E9 - PrmrrSize + Enable/Disable. 0: Disable, define default value of PrmrrSize , 1: enable +**/ + uint32_t PrmrrSize; + +/** Offset 0x02ED - SinitMemorySize + Enable/Disable. 0: Disable, define default value of SinitMemorySize , 1: enable +**/ + uint32_t SinitMemorySize; + +/** Offset 0x02F1 - TxtHeapMemorySize + Enable/Disable. 0: Disable, define default value of TxtHeapMemorySize , 1: enable +**/ + uint32_t TxtHeapMemorySize; + +/** Offset 0x02F5 - TxtDprMemoryBase + Enable/Disable. 0: Disable, define default value of TxtDprMemoryBase , 1: enable +**/ + uint64_t TxtDprMemoryBase; + +/** Offset 0x02FD - TxtDprMemorySize + Enable/Disable. 0: Disable, define default value of TxtDprMemorySize , 1: enable +**/ + uint32_t TxtDprMemorySize; + +/** Offset 0x0301 - ReservedSecurityPreMem + Reserved for Security Pre-Mem + $EN_DIS +**/ + uint8_t ReservedSecurityPreMem[9]; + +/** Offset 0x030A - PCH HPET Enabled + Enable/disable PCH HPET. + $EN_DIS +**/ + uint8_t PchHpetEnable; + +/** Offset 0x030B - PCH HPET BDF valid + Whether the BDF value is valid. 0: Disable; 1: Enable. + $EN_DIS +**/ + uint8_t PchHpetBdfValid; + +/** Offset 0x030C - PCH HPET Bus Number + Bus Number HPETn used as Requestor / Completer ID. Default is 0xF0. +**/ + uint8_t PchHpetBusNumber; + +/** Offset 0x030D - PCH HPET Device Number + Device Number HPETn used as Requestor / Completer ID. Default is 0x1F. +**/ + uint8_t PchHpetDeviceNumber; + +/** Offset 0x030E - PCH HPET Function Number + Function Number HPETn used as Requestor / Completer ID. Default is 0x00. +**/ + uint8_t PchHpetFunctionNumber; + +/** Offset 0x030F - The HPET Base Address + The HPET base address. Default is 0xFED00000. +**/ + uint32_t PchHpetBase; + +/** Offset 0x0313 - Enable PCH HSIO PCIE Rx Set Ctle + Enable PCH PCIe Gen 3 Set CTLE Value. +**/ + uint8_t PchPcieHsioRxSetCtleEnable[24]; + +/** Offset 0x032B - PCH HSIO PCIE Rx Set Ctle Value + PCH PCIe Gen 3 Set CTLE Value. +**/ + uint8_t PchPcieHsioRxSetCtle[24]; + +/** Offset 0x0343 - Enble PCH HSIO PCIE TX Gen 1 Downscale Amplitude Adjustment value override + 0: Disable; 1: Enable. +**/ + uint8_t PchPcieHsioTxGen1DownscaleAmpEnable[24]; + +/** Offset 0x035B - PCH HSIO PCIE Gen 2 TX Output Downscale Amplitude Adjustment value + PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value. +**/ + uint8_t PchPcieHsioTxGen1DownscaleAmp[24]; + +/** Offset 0x0373 - Enable PCH HSIO PCIE TX Gen 2 Downscale Amplitude Adjustment value override + 0: Disable; 1: Enable. +**/ + uint8_t PchPcieHsioTxGen2DownscaleAmpEnable[24]; + +/** Offset 0x038B - PCH HSIO PCIE Gen 2 TX Output Downscale Amplitude Adjustment value + PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value. +**/ + uint8_t PchPcieHsioTxGen2DownscaleAmp[24]; + +/** Offset 0x03A3 - Enable PCH HSIO PCIE TX Gen 3 Downscale Amplitude Adjustment value override + 0: Disable; 1: Enable. +**/ + uint8_t PchPcieHsioTxGen3DownscaleAmpEnable[24]; + +/** Offset 0x03BB - PCH HSIO PCIE Gen 3 TX Output Downscale Amplitude Adjustment value + PCH PCIe Gen 3 TX Output Downscale Amplitude Adjustment value. +**/ + uint8_t PchPcieHsioTxGen3DownscaleAmp[24]; + +/** Offset 0x03D3 - Enable PCH HSIO PCIE Gen 1 TX Output De-Emphasis Adjustment Setting value override + 0: Disable; 1: Enable. +**/ + uint8_t PchPcieHsioTxGen1DeEmphEnable[24]; + +/** Offset 0x03EB - PCH HSIO PCIE Gen 1 TX Output De-Emphasis Adjustment value + PCH PCIe Gen 1 TX Output De-Emphasis Adjustment Setting. +**/ + uint8_t PchPcieHsioTxGen1DeEmph[24]; + +/** Offset 0x0403 - Enable PCH HSIO PCIE Gen 2 TX Output -3.5dB De-Emphasis Adjustment Setting value override + 0: Disable; 1: Enable. +**/ + uint8_t PchPcieHsioTxGen2DeEmph3p5Enable[24]; + +/** Offset 0x041B - PCH HSIO PCIE Gen 2 TX Output -3.5dB De-Emphasis Adjustment value + PCH PCIe Gen 2 TX Output -3.5dB De-Emphasis Adjustment Setting. +**/ + uint8_t PchPcieHsioTxGen2DeEmph3p5[24]; + +/** Offset 0x0433 - Enable PCH HSIO PCIE Gen 2 TX Output -6.0dB De-Emphasis Adjustment Setting value override + 0: Disable; 1: Enable. +**/ + uint8_t PchPcieHsioTxGen2DeEmph6p0Enable[24]; + +/** Offset 0x044B - PCH HSIO PCIE Gen 2 TX Output -6.0dB De-Emphasis Adjustment value + PCH PCIe Gen 2 TX Output -6.0dB De-Emphasis Adjustment Setting. +**/ + uint8_t PchPcieHsioTxGen2DeEmph6p0[24]; + +/** Offset 0x0463 - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override + 0: Disable; 1: Enable. +**/ + uint8_t PchSataHsioRxGen1EqBoostMagEnable[8]; + +/** Offset 0x046B - PCH HSIO SATA 1.5 Gb/s Receiver Equalization Boost Magnitude Adjustment value + PCH HSIO SATA 1.5 Gb/s Receiver Equalization Boost Magnitude Adjustment value. +**/ + uint8_t PchSataHsioRxGen1EqBoostMag[8]; + +/** Offset 0x0473 - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override + 0: Disable; 1: Enable. +**/ + uint8_t PchSataHsioRxGen2EqBoostMagEnable[8]; + +/** Offset 0x047B - PCH HSIO SATA 3.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value + PCH HSIO SATA 3.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value. +**/ + uint8_t PchSataHsioRxGen2EqBoostMag[8]; + +/** Offset 0x0483 - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override + 0: Disable; 1: Enable. +**/ + uint8_t PchSataHsioRxGen3EqBoostMagEnable[8]; + +/** Offset 0x048B - PCH HSIO SATA 6.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value + PCH HSIO SATA 6.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value. +**/ + uint8_t PchSataHsioRxGen3EqBoostMag[8]; + +/** Offset 0x0493 - Enable PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value override + 0: Disable; 1: Enable. +**/ + uint8_t PchSataHsioTxGen1DownscaleAmpEnable[8]; + +/** Offset 0x049B - PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value + PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value. +**/ + uint8_t PchSataHsioTxGen1DownscaleAmp[8]; + +/** Offset 0x04A3 - Enable PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value override + 0: Disable; 1: Enable. +**/ + uint8_t PchSataHsioTxGen2DownscaleAmpEnable[8]; + +/** Offset 0x04AB - PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value + PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value. +**/ + uint8_t PchSataHsioTxGen2DownscaleAmp[8]; + +/** Offset 0x04B3 - Enable PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value override + 0: Disable; 1: Enable. +**/ + uint8_t PchSataHsioTxGen3DownscaleAmpEnable[8]; + +/** Offset 0x04BB - PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value + PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value. +**/ + uint8_t PchSataHsioTxGen3DownscaleAmp[8]; + +/** Offset 0x04C3 - Enable PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting value override + 0: Disable; 1: Enable. +**/ + uint8_t PchSataHsioTxGen1DeEmphEnable[8]; + +/** Offset 0x04CB - PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting + PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting. +**/ + uint8_t PchSataHsioTxGen1DeEmph[8]; + +/** Offset 0x04D3 - Enable PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting value override + 0: Disable; 1: Enable. +**/ + uint8_t PchSataHsioTxGen2DeEmphEnable[8]; + +/** Offset 0x04DB - PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting + PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting. +**/ + uint8_t PchSataHsioTxGen2DeEmph[8]; + +/** Offset 0x04E3 - Enable PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting value override + 0: Disable; 1: Enable. +**/ + uint8_t PchSataHsioTxGen3DeEmphEnable[8]; + +/** Offset 0x04EB - PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting + PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting. +**/ + uint8_t PchSataHsioTxGen3DeEmph[8]; + +/** Offset 0x04F3 - PCH LPC Enhance the port 8xh decoding + Original LPC only decodes one byte of port 80h. + $EN_DIS +**/ + uint8_t PchLpcEnhancePort8xhDecoding; + +/** Offset 0x04F4 - PCH Acpi Base + Power management I/O base address. Default is 0x1800. +**/ + uint16_t PchAcpiBase; + +/** Offset 0x04F6 - PCH Port80 Route + Control where the Port 80h cycles are sent, 0: LPC; 1: PCI. + $EN_DIS +**/ + uint8_t PchPort80Route; + +/** Offset 0x04F7 - Enable SMBus ARP support + Enable SMBus ARP support. + $EN_DIS +**/ + uint8_t SmbusArpEnable; + +/** Offset 0x04F8 - SMBUS Base Address + SMBUS Base Address (IO space). +**/ + uint16_t PchSmbusIoBase; + +/** Offset 0x04FA - Number of RsvdSmbusAddressTable. + The number of elements in the RsvdSmbusAddressTable. +**/ + uint8_t PchNumRsvdSmbusAddresses; + +/** Offset 0x04FB - Point of RsvdSmbusAddressTable + Array of addresses reserved for non-ARP-capable SMBus devices. +**/ + uint32_t RsvdSmbusAddressTablePtr; + +/** Offset 0x04FF - Trace Hub Memory Region 0 + Trace Hub Memory Region 0. +**/ + uint32_t TraceHubMemReg0Size; + +/** Offset 0x0503 - Trace Hub Memory Region 1 + Trace Hub Memory Region 1. +**/ + uint32_t TraceHubMemReg1Size; + +/** Offset 0x0507 - Enable PCIE RP Mask + Enable/disable PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0 + for port1, bit1 for port2, and so on. +**/ + uint32_t PcieRpEnableMask; + +/** Offset 0x050B - SerialIo Uart Debug + Enable SerialIo Uart debug. + 0:Disable, 1:Enable +**/ + uint8_t PcdSerialDebugEnable; + +/** Offset 0x050C - SerialIo Uart Number Selection + Select SerialIo Uart Controller for debug. + 0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2 +**/ + uint8_t PcdSerialIoUartNumber; + +/** Offset 0x050D +**/ + uint8_t ReservedFspmUpd[34]; +} __attribute__((packed)); + +/** Fsp M Test Configuration +**/ +struct FSP_M_TEST_CONFIG { + +/** Offset 0x052F +**/ + uint32_t Signature; + +/** Offset 0x0533 - Skip external display device scanning + Enable: Do not scan for external display device, Disable (Default): Scan external + display devices + $EN_DIS +**/ + uint8_t SkipExtGfxScan; + +/** Offset 0x0534 - Generate BIOS Data ACPI Table + Enable: Generate BDAT for MRC RMT or SA PCIe data. Disable (Default): Do not generate it + $EN_DIS +**/ + uint8_t BdatEnable; + +/** Offset 0x0535 - Detect External Graphics device for LegacyOpROM + Detect and report if external graphics device only support LegacyOpROM or not (to + support CSM auto-enable). Enable(Default)=1, Disable=0 + $EN_DIS +**/ + uint8_t ScanExtGfxForLegacyOpRom; + +/** Offset 0x0536 - Lock PCU Thermal Management registers + Lock PCU Thermal Management registers. Enable(Default)=1, Disable=0 + $EN_DIS +**/ + uint8_t LockPTMregs; + +/** Offset 0x0537 - Enable/Disable DmiVc1 + Enable/Disable DmiVc1. Enable = 1, Disable (Default) = 0 + $EN_DIS +**/ + uint8_t DmiVc1; + +/** Offset 0x0538 - Enable/Disable DmiVcm + Enable/Disable DmiVcm. Enable (Default) = 1, Disable = 0 + $EN_DIS +**/ + uint8_t DmiVcm; + +/** Offset 0x0539 - DMI Max Link Speed + Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1 + Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed + 0:Auto, 1:Gen1, 2:Gen2, 3:Gen3 +**/ + uint8_t DmiMaxLinkSpeed; + +/** Offset 0x053A - DMI Equalization Phase 2 + DMI Equalization Phase 2. (0x0): Disable phase 2, (0x1): Enable phase 2, (0x2)(Default): + AUTO - Use the current default method + 0:Disable phase2, 1:Enable phase2, 2:Auto +**/ + uint8_t DmiGen3EqPh2Enable; + +/** Offset 0x053B - DMI Gen3 Equalization Phase3 + DMI Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method, + HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software + Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static + EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just + Phase1), Disabled(0x4): Bypass Equalization Phase 3 + 0:Auto, 1:HwEq, 2:SwEq, 3:StaticEq, 4:BypassPhase3 +**/ + uint8_t DmiGen3EqPh3Method; + +/** Offset 0x053C - Phase2 EQ enable on the PEG 0:1:0. + Phase2 EQ enable on the PEG 0:1:0. Disabled(0x0): Disable phase 2, Enabled(0x1): + Enable phase 2, Auto(0x2)(Default): Use the current default method + 0:Disable, 1:Enable, 2:Auto +**/ + uint8_t Peg0Gen3EqPh2Enable; + +/** Offset 0x053D - Phase2 EQ enable on the PEG 0:1:1. + Phase2 EQ enable on the PEG 0:1:0. Disabled(0x0): Disable phase 2, Enabled(0x1): + Enable phase 2, Auto(0x2)(Default): Use the current default method + 0:Disable, 1:Enable, 2:Auto +**/ + uint8_t Peg1Gen3EqPh2Enable; + +/** Offset 0x053E - Phase2 EQ enable on the PEG 0:1:2. + Phase2 EQ enable on the PEG 0:1:0. Disabled(0x0): Disable phase 2, Enabled(0x1): + Enable phase 2, Auto(0x2)(Default): Use the current default method + 0:Disable, 1:Enable, 2:Auto +**/ + uint8_t Peg2Gen3EqPh2Enable; + +/** Offset 0x053F - Phase3 EQ method on the PEG 0:1:0. + PEG Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method, + HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software + Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static + EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just + Phase1), Disabled(0x4): Bypass Equalization Phase 3 + 0:Auto, 1:HwEq, 2:SwEq, 3:StaticEq, 4:BypassPhase3 +**/ + uint8_t Peg0Gen3EqPh3Method; + +/** Offset 0x0540 - Phase3 EQ method on the PEG 0:1:1. + PEG Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method, + HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software + Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static + EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just + Phase1), Disabled(0x4): Bypass Equalization Phase 3 + 0:Auto, 1:HwEq, 2:SwEq, 3:StaticEq, 4:BypassPhase3 +**/ + uint8_t Peg1Gen3EqPh3Method; + +/** Offset 0x0541 - Phase3 EQ method on the PEG 0:1:2. + PEG Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method, + HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software + Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static + EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just + Phase1), Disabled(0x4): Bypass Equalization Phase 3 + 0:Auto, 1:HwEq, 2:SwEq, 3:StaticEq, 4:BypassPhase3 +**/ + uint8_t Peg2Gen3EqPh3Method; + +/** Offset 0x0542 - Enable/Disable PEG GEN3 Static EQ Phase1 programming + Program PEG Gen3 EQ Phase1 Static Presets. Disabled(0x0): Disable EQ Phase1 Static + Presets Programming, Enabled(0x1)(Default): Enable EQ Phase1 Static Presets Programming + $EN_DIS +**/ + uint8_t PegGen3ProgramStaticEq; + +/** Offset 0x0543 - PEG Gen3 SwEq Always Attempt + Gen3 Software Equalization will be executed every boot. Disabled(0x0)(Default): + Reuse EQ settings saved/restored from NVRAM whenever possible, Enabled(0x1): Re-test + and generate new EQ values every boot, not recommended + 0:Disable, 1:Enable +**/ + uint8_t Gen3SwEqAlwaysAttempt; + +/** Offset 0x0544 - Select number of TxEq presets to test in the PCIe/DMI SwEq + Select number of TxEq presets to test in the PCIe/DMI SwEq. P7,P3,P5(0x0): Test + Presets 7, 3, and 5, P0-P9(0x1): Test Presets 0-9, Auto(0x2)(Default): Use the + current default method (Default)Auto will test Presets 7, 3, and 5. It is possible + for this default to change over time;using Auto will ensure Reference Code always + uses the latest default settings + 0:P7 P3 P5, 1:P0 to P9, 2:Auto +**/ + uint8_t Gen3SwEqNumberOfPresets; + +/** Offset 0x0545 - Enable use of the Voltage Offset and Centering Test in the PCIe SwEq + Enable use of the Voltage Offset and Centering Test in the PCIe Software Equalization + Algorithm. Disabled(0x0): Disable VOC Test, Enabled(0x1): Enable VOC Test, Auto(0x2)(Default): + Use the current default + 0:Disable, 1:Enable, 2:Auto +**/ + uint8_t Gen3SwEqEnableVocTest; + +/** Offset 0x0546 - PPCIe Rx Compliance Testing Mode + Disabled(0x0)(Default): Normal Operation - Disable PCIe Rx Compliance testing, Enabled(0x1): + PCIe Rx Compliance Test Mode - PEG controller is in Rx Compliance Testing Mode; + it should only be set when doing PCIe compliance testing + $EN_DIS +**/ + uint8_t PegRxCemTestingMode; + +/** Offset 0x0547 - PCIe Rx Compliance Loopback Lane When PegRxCemTestingMode is Enabled + the specificied Lane (0 - 15) will be used for RxCEMLoopback. Default is Lane 0 +**/ + uint8_t PegRxCemLoopbackLane; + +/** Offset 0x0548 - Generate PCIe BDAT Margin Table + Set this policy to enable the generation and addition of PCIe margin data to the + BDAT table. Disabled(0x0)(Default): Normal Operation - Disable PCIe BDAT margin + data generation, Enable(0x1): Generate PCIe BDAT margin data + $EN_DIS +**/ + uint8_t PegGenerateBdatMarginTable; + +/** Offset 0x0549 - PCIe Non-Protocol Awareness for Rx Compliance Testing + Set this policy to enable the generation and addition of PCIe margin data to the + BDAT table. Disabled(0x0)(Default): Normal Operation - Disable non-protocol awareness, + Enable(0x1): Non-Protocol Awareness Enabled - Enable non-protocol awareness for + compliance testing + $EN_DIS +**/ + uint8_t PegRxCemNonProtocolAwareness; + +/** Offset 0x054A - PCIe Override RxCTLE + Disable(0x0)(Default): Normal Operation - RxCTLE adaptive behavior enabled, Enable(0x1): + Override RxCTLE - Disable RxCTLE adaptive behavior to keep the configured RxCTLE + peak values unmodified + $EN_DIS +**/ + uint8_t PegGen3RxCtleOverride; + +/** Offset 0x054B - Rsvd + Disable(0x0)(Default): Normal Operation - RxCTLE adaptive behavior enabled, Enable(0x1): + Override RxCTLE - Disable RxCTLE adaptive behavior to keep the configured RxCTLE + peak values unmodified + $EN_DIS +**/ + uint8_t PegGen3Rsvd; + +/** Offset 0x054C - PEG Gen3 Root port preset values per lane + Used for programming PEG Gen3 preset values per lane. Range: 0-9, 8 is default for each lane +**/ + uint8_t PegGen3RootPortPreset[16]; + +/** Offset 0x055C - PEG Gen3 End port preset values per lane + Used for programming PEG Gen3 preset values per lane. Range: 0-9, 7 is default for each lane +**/ + uint8_t PegGen3EndPointPreset[16]; + +/** Offset 0x056C - PEG Gen3 End port Hint values per lane + Used for programming PEG Gen3 Hint values per lane. Range: 0-6, 2 is default for each lane +**/ + uint8_t PegGen3EndPointHint[16]; + +/** Offset 0x057C - Jitter Dwell Time for PCIe Gen3 Software Equalization + Range: 0-65535, default is 1000. @warning Do not change from the default +**/ + uint16_t Gen3SwEqJitterDwellTime; + +/** Offset 0x057E - Jitter Error Target for PCIe Gen3 Software Equalization + Range: 0-65535, default is 1. @warning Do not change from the default +**/ + uint16_t Gen3SwEqJitterErrorTarget; + +/** Offset 0x0580 - VOC Dwell Time for PCIe Gen3 Software Equalization + Range: 0-65535, default is 10000. @warning Do not change from the default +**/ + uint16_t Gen3SwEqVocDwellTime; + +/** Offset 0x0582 - VOC Error Target for PCIe Gen3 Software Equalization + Range: 0-65535, default is 2. @warning Do not change from the default +**/ + uint16_t Gen3SwEqVocErrorTarget; + +/** Offset 0x0584 - Panel Power Enable + Control for enabling/disabling VDD force bit (Required only for early enabling of + eDP panel). 0=Disable, 1(Default)=Enable + $EN_DIS +**/ + uint8_t PanelPowerEnable; + +/** Offset 0x0585 - SaPreMemTestRsvd + Reserved for SA Pre-Mem Test + $EN_DIS +**/ + uint8_t SaPreMemTestRsvd[16]; + +/** Offset 0x0595 - TotalFlashSize + Enable/Disable. 0: Disable, define default value of TotalFlashSize , 1: enable +**/ + uint16_t TotalFlashSize; + +/** Offset 0x0597 - BiosSize + Enable/Disable. 0: Disable, define default value of BiosSize , 1: enable +**/ + uint16_t BiosSize; + +/** Offset 0x0599 - BiosAcmBase + Enable/Disable. 0: Disable, define default value of BiosAcmBase , 1: enable +**/ + uint64_t BiosAcmBase; + +/** Offset 0x05A1 - BiosAcmSize + Enable/Disable. 0: Disable, define default value of BiosAcmSize , 1: enable +**/ + uint32_t BiosAcmSize; + +/** Offset 0x05A5 - TgaSize + Enable/Disable. 0: Disable, define default value of TgaSize , 1: enable +**/ + uint32_t TgaSize; + +/** Offset 0x05A9 - TxtLcpPdBase + Enable/Disable. 0: Disable, define default value of TxtLcpPdBase , 1: enable +**/ + uint64_t TxtLcpPdBase; + +/** Offset 0x05B1 - TxtLcpPdSize + Enable/Disable. 0: Disable, define default value of TxtLcpPdSize , 1: enable +**/ + uint64_t TxtLcpPdSize; + +/** Offset 0x05B9 - PCH Dci Enable + Enable/disable PCH Dci. + $EN_DIS +**/ + uint8_t PchDciEn; + +/** Offset 0x05BA - PCH Dci Auto Detect + Enable/disable PCH Dci AUTO mode. + $EN_DIS +**/ + uint8_t PchDciAutoDetect; + +/** Offset 0x05BB - Smbus dynamic power gating + Disable or Enable Smbus dynamic power gating. + $EN_DIS +**/ + uint8_t SmbusDynamicPowerGating; + +/** Offset 0x05BC - Disable and Lock Watch Dog Register + Set 1 to clear WDT status, then disable and lock WDT registers. + $EN_DIS +**/ + uint8_t WdtDisableAndLock; + +/** Offset 0x05BD - SMBUS SPD Write Disable + Set/Clear Smbus SPD Write Disable. 0: leave SPD Write Disable bit; 1: set SPD Write + Disable bit. For security recommendations, SPD write disable bit must be set. + $EN_DIS +**/ + uint8_t SmbusSpdWriteDisable; + +/** Offset 0x05BE - ChipsetInit HECI message + Enable/Disable. 0: Disable, 1: enable, Enable or disable ChipsetInit HECI message. + If disabled, it prevents from sending ChipsetInit HECI message. + $EN_DIS +**/ + uint8_t ChipsetInitMessage; + +/** Offset 0x05BF - Bypass ChipsetInit sync reset. + 0: disable, 1: enable, Set Enable to bypass the reset after ChipsetInit HECI message. + $EN_DIS +**/ + uint8_t BypassPhySyncReset; + +/** Offset 0x05C0 - Force ME DID Init Status + Test, 0: disable, 1: Success, 2: No Memory in Channels, 3: Memory Init Error, 4: + Memory not preserved across reset, Set ME DID init stat value + $EN_DIS +**/ + uint8_t DidInitStat; + +/** Offset 0x05C1 - CPU Replaced Polling Disable + Test, 0: disable, 1: enable, Setting this option disables CPU replacement polling loop + $EN_DIS +**/ + uint8_t DisableCpuReplacedPolling; + +/** Offset 0x05C2 - ME DID Message + Test, 0: disable, 1: enable, Enable/Disable ME DID Message (disable will prevent + the DID message from being sent) + $EN_DIS +**/ + uint8_t SendDidMsg; + +/** Offset 0x05C3 - Retry mechanism for HECI APIs + Test, 0: disable, 1: enable, Enable/Disable HECI retry. + $EN_DIS +**/ + uint8_t DisableHeciRetry; + +/** Offset 0x05C4 - Check HECI message before send + Test, 0: disable, 1: enable, Enable/Disable message check. + $EN_DIS +**/ + uint8_t DisableMessageCheck; + +/** Offset 0x05C5 - Skip MBP HOB + Test, 0: disable, 1: enable, Enable/Disable MOB HOB. + $EN_DIS +**/ + uint8_t SkipMbpHob; + +/** Offset 0x05C6 - HECI2 Interface Communication + Test, 0: disable, 1: enable, Adds or Removes HECI2 Device from PCI space. + $EN_DIS +**/ + uint8_t HeciCommunication2; + +/** Offset 0x05C7 - Enable KT device + Test, 0: disable, 1: enable, Enable or Disable KT device. + $EN_DIS +**/ + uint8_t KtDeviceEnable; + +/** Offset 0x05C8 - Enable IDEr + Test, 0: disable, 1: enable, Enable or Disable IDEr. + $EN_DIS +**/ + uint8_t IderDeviceEnable; + +/** Offset 0x05C9 +**/ + uint8_t ReservedFspmTestUpd[17]; +} __attribute__((packed)); + +/** Fsp M UPD Configuration +**/ +struct FSPM_UPD { + +/** Offset 0x0000 +**/ + struct FSP_UPD_HEADER FspUpdHeader; + +/** Offset 0x0020 +**/ + struct FSPM_ARCH_UPD FspmArchUpd; + +/** Offset 0x0040 +**/ + struct FSP_M_CONFIG FspmConfig; + +/** Offset 0x052F +**/ + struct FSP_M_TEST_CONFIG FspmTestConfig; + +/** Offset 0x05DA +**/ + uint8_t UnusedUpdSpace8[156]; + +/** Offset 0x0676 +**/ + uint16_t UpdTerminator; +} __attribute__((packed)); + +#endif diff --git a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/soc/fsp/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/soc/fsp/FspsUpd.h new file mode 100644 index 0000000000..aae3cf5423 --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/soc/fsp/FspsUpd.h @@ -0,0 +1,2924 @@ +/** @file + +Copyright (c) 2016, Intel Corporation. All rights reserved.<BR> + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + + This file is automatically generated. Please do NOT modify !!! + +**/ + +#ifndef __FSPSUPD_H__ +#define __FSPSUPD_H__ + +#include "FspUpd.h" +#include <fsp/upd.h> + + +#include "CpuConfigFspData.h" +/// +/// Azalia Header structure +/// +struct AZALIA_HEADER { + uint16_t VendorId; ///< Codec Vendor ID + uint16_t DeviceId; ///< Codec Device ID + uint8_t RevisionId; ///< Revision ID of the codec. 0xFF matches any revision. + uint8_t SdiNum; ///< SDI number, 0xFF matches any SDI. + uint16_t DataDwords; ///< Number of data DWORDs pointed by the codec data buffer. + uint32_t Reserved; ///< Reserved for future use. Must be set to 0. +} __attribute__((packed)); + +/// +/// Audio Azalia Verb Table structure +/// +struct AUDIO_AZALIA_VERB_TABLE { + struct AZALIA_HEADER Header; ///< AZALIA PCH header + uint32_t *Data; ///< Pointer to the data buffer. Its length is specified in the header +} __attribute__((packed)); + +/// +/// Refer to the definition of PCH_INT_PIN +/// +enum SI_PCH_INT_PIN{ + SiPchNoInt, ///< No Interrupt Pin + SiPchIntA, + SiPchIntB, + SiPchIntC, + SiPchIntD +}; + +/// +/// The PCH_DEVICE_INTERRUPT_CONFIG block describes interrupt pin, IRQ and interrupt mode for PCH device. +/// +struct SI_PCH_DEVICE_INTERRUPT_CONFIG{ + uint8_t Device; ///< Device number + uint8_t Function; ///< Device function + uint8_t IntX; ///< Interrupt pin: INTA-INTD (see SI_PCH_INT_PIN) + uint8_t Irq; ///< IRQ to be set for device. +} __attribute__((packed));; + +#define SI_PCH_MAX_DEVICE_INTERRUPT_CONFIG 64 ///< Number of all PCH devices + +/** Fsp S Configuration +**/ +struct FSP_S_CONFIG { + +/** Offset 0x0020 - Logo Pointer + Points to PEI Display Logo Image + 0 : 0 +**/ + uint32_t LogoPtr; + +/** Offset 0x0024 - Logo Size + Size of PEI Display Logo Image + 0 : 0 +**/ + uint32_t LogoSize; + +/** Offset 0x0028 - Graphics Configuration Ptr + Points to VBT + 0 : 0 +**/ + uint32_t GraphicsConfigPtr; + +/** Offset 0x002C - Enable Device 4 + Enable/disable Device 4 + $EN_DIS +**/ + uint8_t Device4Enable; + +/** Offset 0x002D - Enable Intel HD Audio (Azalia) + Enable/disable Azalia controller. + $EN_DIS +**/ + uint8_t PchHdaEnable; + +/** Offset 0x002E - Enable HD Audio DSP + Enable/disable HD Audio DSP feature. + $EN_DIS +**/ + uint8_t PchHdaDspEnable; + +/** Offset 0x002F - Select HDAudio IoBuffer Ownership + Indicates the ownership of the I/O buffer between Intel HD Audio link vs I2S0 / + I2S port. 0: Intel HD-Audio link owns all the I/O buffers. 1: Intel HD-Audio link + owns 4 of the I/O buffers for 1 HD-Audio codec connection, and I2S1 port owns 4 + of the I/O buffers for 1 I2S codec connection. 2: Reserved. 3: I2S0 and I2S1 ports + own all the I/O buffers. + 0:HD-A Link, 1:Shared HD-A Link and I2S Port, 3:I2S Ports +**/ + uint8_t PchHdaIoBufferOwnership; + +/** Offset 0x0030 - Enable CIO2 Controller + Enable/disable SKYCAM CIO2 Controller. + $EN_DIS +**/ + uint8_t PchCio2Enable; + +/** Offset 0x0031 - Enable eMMC Controller + Enable/disable eMMC Controller. + $EN_DIS +**/ + uint8_t ScsEmmcEnabled; + +/** Offset 0x0032 - Enable eMMC HS400 Mode + Enable eMMC HS400 Mode. + $EN_DIS +**/ + uint8_t ScsEmmcHs400Enabled; + +/** Offset 0x0033 - Enable SdCard Controller + Enable/disable SD Card Controller. + $EN_DIS +**/ + uint8_t ScsSdCardEnabled; + +/** Offset 0x0034 - Enable PCH ISH Controller + Enable/disable ISH Controller. + $EN_DIS +**/ + uint8_t PchIshEnable; + +/** Offset 0x0035 - Show SPI controller + Enable/disable to show SPI controller. + $EN_DIS +**/ + uint8_t ShowSpiController; + +/** Offset 0x0036 +**/ + uint16_t UnusedUpdSpace0; + +/** Offset 0x0038 - MicrocodeRegionBase + Memory Base of Microcode Updates +**/ + uint32_t MicrocodeRegionBase; + +/** Offset 0x003C - MicrocodeRegionSize + Size of Microcode Updates +**/ + uint32_t MicrocodeRegionSize; + +/** Offset 0x0040 - Turbo Mode + Enable/Disable Turbo mode. 0: disable, 1: enable + $EN_DIS +**/ + uint8_t TurboMode; + +/** Offset 0x0041 - Enable SATA SALP Support + Enable/disable SATA Aggressive Link Power Management. + $EN_DIS +**/ + uint8_t SataSalpSupport; + +/** Offset 0x0042 - Enable SATA ports + Enable/disable SATA ports. One byte for each port, byte0 for port0, byte1 for port1, + and so on. +**/ + uint8_t SataPortsEnable[8]; + +/** Offset 0x004A - Enable SATA DEVSLP Feature + Enable/disable SATA DEVSLP per port. 0 is disable, 1 is enable. One byte for each + port, byte0 for port0, byte1 for port1, and so on. +**/ + uint8_t SataPortsDevSlp[8]; + +/** Offset 0x0052 - Enable USB2 ports + Enable/disable per USB2 ports. One byte for each port, byte0 for port0, byte1 for + port1, and so on. +**/ + uint8_t PortUsb20Enable[16]; + +/** Offset 0x0062 - Enable USB3 ports + Enable/disable per USB3 ports. One byte for each port, byte0 for port0, byte1 for + port1, and so on. +**/ + uint8_t PortUsb30Enable[10]; + +/** Offset 0x006C - Enable xDCI controller + Enable/disable to xDCI controller. + $EN_DIS +**/ + uint8_t XdciEnable; + +/** Offset 0x006D - Enable XHCI SSIC Eanble + Enable/disable XHCI SSIC port. + $EN_DIS +**/ + uint8_t SsicPortEnable; + +/** Offset 0x006E +**/ + uint8_t UnusedUpdSpace1[1]; + +/** Offset 0x006F - Enable SerialIo Device Mode + 0:Disabled, 1:ACPI Mode, 2:PCI Mode, 3:Hidden mode, 4:Legacy UART mode - Enable/disable + SerialIo I2C0,I2C1,I2C2,I2C3,I2C4,I2C5,SPI0,SPI1,UART0,UART1,UART2 device mode + respectively. One byte for each controller, byte0 for I2C0, byte1 for I2C1, and so on. +**/ + uint8_t SerialIoDevMode[11]; + +/** Offset 0x007A - Address of PCH_DEVICE_INTERRUPT_CONFIG table. + The address of the table of PCH_DEVICE_INTERRUPT_CONFIG. +**/ + uint32_t DevIntConfigPtr; + +/** Offset 0x007E - Number of DevIntConfig Entry + Number of Device Interrupt Configuration Entry. If this is not zero, the DevIntConfigPtr + must not be NULL. +**/ + uint8_t NumOfDevIntConfig; + +/** Offset 0x007F - PIRQx to IRQx Map Config + PIRQx to IRQx mapping. The valid value is 0x00 to 0x0F for each. First byte is for + PIRQA, second byte is for PIRQB, and so on. The setting is only available in Legacy + 8259 PCI mode. +**/ + uint8_t PxRcConfig[8]; + +/** Offset 0x0087 - Select GPIO IRQ Route + GPIO IRQ Select. The valid value is 14 or 15. + 0 : 0xFF +**/ + uint8_t GpioIrqRoute; + +/** Offset 0x0088 - Select SciIrqSelect + SCI IRQ Select. The valid value is 9, 10, 11, and 20, 21, 22, 23 for APIC only. + 0 : 0xFF +**/ + uint8_t SciIrqSelect; + +/** Offset 0x0089 - Select TcoIrqSelect + TCO IRQ Select. The valid value is 9, 10, 11, 20, 21, 22, 23. + 0 : 0xFF +**/ + uint8_t TcoIrqSelect; + +/** Offset 0x008A - Enable/Disable Tco IRQ + Enable/disable TCO IRQ + $EN_DIS +**/ + uint8_t TcoIrqEnable; + +/** Offset 0x008B - PCH HDA Verb Table Entry Number + Number of Entries in Verb Table. +**/ + uint8_t PchHdaVerbTableEntryNum; + +/** Offset 0x008C - PCH HDA Verb Table Pointer + Pointer to Array of pointers to Verb Table. +**/ + uint32_t PchHdaVerbTablePtr; + +/** Offset 0x0090 +**/ + uint8_t UnusedUpdSpace2; + +/** Offset 0x0091 - Enable SATA + Enable/disable SATA controller. + $EN_DIS +**/ + uint8_t SataEnable; + +/** Offset 0x0092 - SATA Mode + Select SATA controller working mode. + 0:AHCI, 1:RAID +**/ + uint8_t SataMode; + +/** Offset 0x0093 - USB Per Port HS Preemphasis Bias + USB Per Port HS Preemphasis Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV, + 100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV. One byte for each port. +**/ + uint8_t Usb2AfePetxiset[16]; + +/** Offset 0x00A3 - USB Per Port HS Transmitter Bias + USB Per Port HS Transmitter Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV, + 100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV, One byte for each port. +**/ + uint8_t Usb2AfeTxiset[16]; + +/** Offset 0x00B3 - USB Per Port HS Transmitter Emphasis + USB Per Port HS Transmitter Emphasis. 00b - Emphasis OFF, 01b - De-emphasis ON, + 10b - Pre-emphasis ON, 11b - Pre-emphasis & De-emphasis ON. One byte for each port. +**/ + uint8_t Usb2AfePredeemp[16]; + +/** Offset 0x00C3 - USB Per Port Half Bit Pre-emphasis + USB Per Port Half Bit Pre-emphasis. 1b - half-bit pre-emphasis, 0b - full-bit pre-emphasis. + One byte for each port. +**/ + uint8_t Usb2AfePehalfbit[16]; + +/** Offset 0x00D3 - Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment + Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment. Each value + in arrary can be between 0-1. One byte for each port. +**/ + uint8_t Usb3HsioTxDeEmphEnable[10]; + +/** Offset 0x00DD - USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting + USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting, HSIO_TX_DWORD5[21:16], + <b>Default = 29h</b> (approximately -3.5dB De-Emphasis). One byte for each port. +**/ + uint8_t Usb3HsioTxDeEmph[10]; + +/** Offset 0x00E7 - Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment + Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment, Each value + in arrary can be between 0-1. One byte for each port. +**/ + uint8_t Usb3HsioTxDownscaleAmpEnable[10]; + +/** Offset 0x00F1 - USB 3.0 TX Output Downscale Amplitude Adjustment + USB 3.0 TX Output Downscale Amplitude Adjustment, HSIO_TX_DWORD8[21:16], <b>Default + = 00h</b>. One byte for each port. +**/ + uint8_t Usb3HsioTxDownscaleAmp[10]; + +/** Offset 0x00FB - Enable LAN + Enable/disable LAN controller. + $EN_DIS +**/ + uint8_t PchLanEnable; + +/** Offset 0x00FC +**/ + uint8_t UnusedUpdSpace3[24]; + +/** Offset 0x0114 - Enable PCIE RP CLKREQ Support + Enable/disable PCIE Root Port CLKREQ support. 0: disable, 1: enable. One byte for + each port, byte0 for port1, byte1 for port2, and so on. +**/ + uint8_t PcieRpClkReqSupport[24]; + +/** Offset 0x012C - Configure CLKREQ Number + Configure Root Port CLKREQ Number if CLKREQ is supported. Each value in arrary can + be between 0-6. One byte for each port, byte0 for port1, byte1 for port2, and so on. +**/ + uint8_t PcieRpClkReqNumber[24]; + +/** Offset 0x0144 +**/ + uint8_t UnusedUpdSpace4[5]; + +/** Offset 0x0149 - HECI3 state + The HECI3 state from Mbp for reference in S3 path or when MbpHob is not installed. + 0: disable, 1: enable + $EN_DIS +**/ + uint8_t Heci3Enabled; + +/** Offset 0x014A +**/ + uint8_t UnusedUpdSpace5[9]; + +/** Offset 0x0153 - AMT Switch + Enable/Disable. 0: Disable, 1: enable, Enable or disable AMT functionality. + $EN_DIS +**/ + uint8_t AmtEnabled; + +/** Offset 0x0154 - WatchDog Timer Switch + Enable/Disable. 0: Disable, 1: enable, Enable or disable WatchDog timer. + $EN_DIS +**/ + uint8_t WatchDog; + +/** Offset 0x0155 - ASF Switch + Enable/Disable. 0: Disable, 1: enable, Enable or disable ASF functionality. + $EN_DIS +**/ + uint8_t AsfEnabled; + +/** Offset 0x0156 - Manageability Mode set by Mebx + Enable/Disable. 0: Disable, 1: enable, Enable or disable Manageability Mode. + $EN_DIS +**/ + uint8_t ManageabilityMode; + +/** Offset 0x0157 - PET Progress + Enable/Disable. 0: Disable, 1: enable, Enable/Disable PET Events Progress to receive + PET Events. + $EN_DIS +**/ + uint8_t FwProgress; + +/** Offset 0x0158 - SOL Switch + Enable/Disable. 0: Disable, 1: enable, Serial Over Lan enable/disable state by Mebx + $EN_DIS +**/ + uint8_t AmtSolEnabled; + +/** Offset 0x0159 - OS Timer + 16 bits Value, Set OS watchdog timer. + $EN_DIS +**/ + uint16_t WatchDogTimerOs; + +/** Offset 0x015B - BIOS Timer + 16 bits Value, Set BIOS watchdog timer. + $EN_DIS +**/ + uint16_t WatchDogTimerBios; + +/** Offset 0x015D +**/ + uint8_t UnusedUpdSpace6[163]; + +/** Offset 0x0200 - Enable/Disable SA CRID + Enable: SA CRID, Disable (Default): SA CRID + $EN_DIS +**/ + uint8_t CridEnable; + +/** Offset 0x0201 - Subsystem Vendor ID for SA devices + Subsystem ID that will be programmed to SA devices: Default SubSystemVendorId=0x8086 +**/ + uint16_t DefaultSvid; + +/** Offset 0x0203 - Subsystem Device ID for SA devices + Subsystem ID that will be programmed to SA devices: Default SubSystemId=0x2015 +**/ + uint16_t DefaultSid; + +/** Offset 0x0205 - DMI ASPM + 0=Disable, 2(Default)=L1 + 0:Disable, 2:L1 +**/ + uint8_t DmiAspm; + +/** Offset 0x0206 - PCIe DeEmphasis control per root port + 0: -6dB, 1(Default): -3.5dB + 0:Disable, 2:L1 +**/ + uint8_t PegDeEmphasis[3]; + +/** Offset 0x0209 - PCIe Slot Power Limit value per root port + Slot power limit value per root port +**/ + uint8_t PegSlotPowerLimitValue[3]; + +/** Offset 0x020C - PCIe Slot Power Limit scale per root port + Slot power limit scale per root port + 0:1.0x, 1:0.1x, 2:0.01x, 3:0x001x +**/ + uint8_t PegSlotPowerLimitScale[3]; + +/** Offset 0x020F - PCIe Physical Slot Number per root port + Physical Slot Number per root port +**/ + uint16_t PegPhysicalSlotNumber[3]; + +/** Offset 0x0215 - Enable/Disable PavpEnable + Enable(Default): Enable PavpEnable, Disable: Disable PavpEnable + $EN_DIS +**/ + uint8_t PavpEnable; + +/** Offset 0x0216 - CdClock Frequency selection + 0=308.57 Mhz, 1=337.5 Mhz, 2=432 Mhz, 3=450 Mhz, 4=540 Mhz, 5=617.14 Mhz, 6(Default)= 675 Mhz + 0: 308.57 Mhz, 1: 337.5 Mhz, 2: 432 Mhz, 3: 450 Mhz, 4: 540 Mhz, 5: 617.14 Mhz, + 6: 675 Mhz +**/ + uint8_t CdClock; + +/** Offset 0x0217 - Enable/Disable PeiGraphicsPeimInit + Enable: Enable PeiGraphicsPeimInit, Disable(Default): Disable PeiGraphicsPeimInit + $EN_DIS +**/ + uint8_t PeiGraphicsPeimInit; + +/** Offset 0x0218 - Enable/Disable SA IMGU(SKYCAM) + Enable(Default): Enable SA IMGU(SKYCAM), Disable: Disable SA IMGU(SKYCAM) + $EN_DIS +**/ + uint8_t SaImguEnable; + +/** Offset 0x0219 - Enable or disable GMM device + 0=Disable, 1(Default)=Enable + $EN_DIS +**/ + uint8_t GmmEnable; + +/** Offset 0x021A - State of X2APIC_OPT_OUT bit in the DMAR table + 0=Disable/Clear, 1(Default)=Enable/Set + $EN_DIS +**/ + uint8_t X2ApicOptOut; + +/** Offset 0x021B - Base addresses for VT-d function MMIO access + Base addresses for VT-d MMIO access per VT-d engine +**/ + uint32_t VtdBaseAddress[2]; + +/** Offset 0x0223 +**/ + uint8_t UnusedUpdSpace7[20]; + +/** Offset 0x0237 - SaPostMemProductionRsvd + Reserved for SA Post-Mem Production + $EN_DIS +**/ + uint8_t SaPostMemProductionRsvd[16]; + +/** Offset 0x0247 +**/ + uint8_t UnusedUpdSpace8[7]; + +/** Offset 0x024E - Power State 3 enable/disable + PCODE MMIO Mailbox: Power State 3 enable/disable; 0: Disable; <b>1: Enable</b>. + For all VR Indexes +**/ + uint8_t Psi3Enable[5]; + +/** Offset 0x0253 - Power State 4 enable/disable + PCODE MMIO Mailbox: Power State 4 enable/disable; 0: Disable; <b>1: Enable</b>.For + all VR Indexes +**/ + uint8_t Psi4Enable[5]; + +/** Offset 0x0258 - Imon slope correction + PCODE MMIO Mailbox: Imon slope correction. Specified in 1/100 increment values. + Range is 0-200. 125 = 1.25. <b>0: Auto</b>.For all VR Indexes +**/ + uint8_t ImonSlope[5]; + +/** Offset 0x025D - Imon offset correction + PCODE MMIO Mailbox: Imon offset correction. Value is a 2's complement signed integer. + Units 1/1000, Range 0-63999. For an offset = 12.580, use 12580. <b>0: Auto</b> +**/ + uint8_t ImonOffset[5]; + +/** Offset 0x0262 - Enable/Disable BIOS configuration of VR + Enable/Disable BIOS configuration of VR; <b>0: Disable</b>; 1: Enable.For all VR Indexes +**/ + uint8_t VrConfigEnable[5]; + +/** Offset 0x0267 - Thermal Design Current enable/disable + PCODE MMIO Mailbox: Thermal Design Current enable/disable; <b>0: Disable</b>; 1: + Enable.For all VR Indexes +**/ + uint8_t TdcEnable[5]; + +/** Offset 0x026C - HECI3 state + PCODE MMIO Mailbox: Thermal Design Current time window. Defined in milli seconds. + Valid Values 1 - 1ms , 2 - 2ms , 3 - 3ms , 4 - 4ms , 5 - 5ms , 6 - 6ms , 7 - 7ms + , 8 - 8ms , 10 - 10ms.For all VR Indexe +**/ + uint8_t TdcTimeWindow[5]; + +/** Offset 0x0271 - Thermal Design Current Lock + PCODE MMIO Mailbox: Thermal Design Current Lock; <b>0: Disable</b>; 1: Enable.For + all VR Indexes +**/ + uint8_t TdcLock[5]; + +/** Offset 0x0276 - Platform Psys slope correction + PCODE MMIO Mailbox: Platform Psys slope correction. <b>0 - Auto</b> Specified in + 1/100 increment values. Range is 0-200. 125 = 1.25 + 0x0:0xFF +**/ + uint8_t PsysSlope; + +/** Offset 0x0277 - Platform Psys offset correction + PCODE MMIO Mailbox: Platform Psys offset correction. <b>0 - Auto</b> Units 1/4, + Range 0-255. Value of 100 = 100/4 = 25 offset + 0x0:0xFF +**/ + uint8_t PsysOffset; + +/** Offset 0x0278 - Acoustic Noise Mitigation feature + Enable or Disable Acoustic Noise Mitigation feature. <b>0: Disabled</b>; 1: Enabled + 0x0:0xFF +**/ + uint8_t AcousticNoiseMitigation; + +/** Offset 0x0279 - Disable Fast Slew Rate for Deep Package C States for VR IA domain + Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation + feature enabled. <b>0: False</b>; 1: True + 0x0:0xFF +**/ + uint8_t FastPkgCRampDisableIa; + +/** Offset 0x027A - Slew Rate configuration for Deep Package C States for VR IA domain + Slew Rate configuration for Deep Package C States for VR IA domain based on Acoustic + Noise Mitigation feature enabled. <b>0: Fast/2</b>; 1: Fast/4; 2: Fast/8; 3: Fast/16 + 0x0:0xFF +**/ + uint8_t SlowSlewRateForIa; + +/** Offset 0x027B - Slew Rate configuration for Deep Package C States for VR GT domain + Slew Rate configuration for Deep Package C States for VR GT domain based on Acoustic + Noise Mitigation feature enabled. <b>0: Fast/2</b>; 1: Fast/4; 2: Fast/8; 3: Fast/16 + 0x0:0xFF +**/ + uint8_t SlowSlewRateForGt; + +/** Offset 0x027C - Slew Rate configuration for Deep Package C States for VR SA domain + Slew Rate configuration for Deep Package C States for VR SA domain based on Acoustic + Noise Mitigation feature enabled. <b>0: Fast/2</b>; 1: Fast/4; 2: Fast/8; 3: Fast/16 + 0x0:0xFF +**/ + uint8_t SlowSlewRateForSa; + +/** Offset 0x027D +**/ + uint8_t UnusedUpdSpace9[8]; + +/** Offset 0x0285 - Thermal Design Current current limit + PCODE MMIO Mailbox: Thermal Design Current current limit. Specified in 1/8A units. + Range is 0-4095. 1000 = 125A. <b>0: Auto</b>. For all VR Indexes +**/ + uint16_t TdcPowerLimit[5]; + +/** Offset 0x028F +**/ + uint8_t UnusedUpdSpace10[10]; + +/** Offset 0x0299 - AcLoadline + PCODE MMIO Mailbox: AcLoadline in 1/100 mOhms (ie. 1250 = 12.50 mOhm); Range is + 0-6249. <b>Intel Recommended Defaults vary by domain and SKU. +**/ + uint16_t AcLoadline[5]; + +/** Offset 0x02A3 - DcLoadline + PCODE MMIO Mailbox: DcLoadline in 1/100 mOhms (ie. 1250 = 12.50 mOhm); Range is + 0-6249.<b>Intel Recommended Defaults vary by domain and SKU.</b> +**/ + uint16_t DcLoadline[5]; + +/** Offset 0x02AD - Power State 1 Threshold current + PCODE MMIO Mailbox: Power State 1 current cuttof in 1/4 Amp increments. Range is + 0-128A. Default Value = 20A. +**/ + uint16_t Psi1Threshold[5]; + +/** Offset 0x02B7 - Power State 2 Threshold current + PCODE MMIO Mailbox: Power State 2 current cuttof in 1/4 Amp increments. Range is + 0-128A. Default Value = 5A. +**/ + uint16_t Psi2Threshold[5]; + +/** Offset 0x02C1 - Power State 3 Threshold current + PCODE MMIO Mailbox: Power State 3 current cuttof in 1/4 Amp increments. Range is + 0-128A. Default Value = 1A. +**/ + uint16_t Psi3Threshold[5]; + +/** Offset 0x02CB - Icc Max limit + PCODE MMIO Mailbox: VR Icc Max limit. 0-255A in 1/4 A units. 400 = 100A +**/ + uint16_t IccMax[5]; + +/** Offset 0x02D5 - VR Voltage Limit + PCODE MMIO Mailbox: VR Voltage Limit. Range is 0-7999mV. +**/ + uint16_t VrVoltageLimit[5]; + +/** Offset 0x02DF - Disable Fast Slew Rate for Deep Package C States for VR GT domain + Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation + feature enabled. <b>0: False</b>; 1: True + 0x0:0xFF +**/ + uint8_t FastPkgCRampDisableGt; + +/** Offset 0x02E0 - Disable Fast Slew Rate for Deep Package C States for VR SA domain + Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation + feature enabled. <b>0: False</b>; 1: True + 0x0:0xFF +**/ + uint8_t FastPkgCRampDisableSa; + +/** Offset 0x02E1 +**/ + uint8_t UnusedUpdSpace11; + +/** Offset 0x02E2 - Enable VR specific mailbox command + VR specific mailbox commands. <b>00b - no VR specific command sent.</b> 01b - A + VR mailbox command specifically for the MPS IMPV8 VR will be sent. 10b - VR specific + command sent for PS4 exit issue. 11b - Reserved. + $EN_DIS +**/ + uint8_t SendVrMbxCmd; + +/** Offset 0x02E3 - Select VR specific mailbox command to send + VR specific mailbox commands. <b>000b - no VR specific command sent.</b> 001b - + VR mailbox command specifically for the MPS IMPV8 VR will be sent. 010b - VR specific + command sent for PS4 exit issue. 100b - VR specific command sent for MPS VR decay issue. +**/ + uint8_t SendVrMbxCmd1; + +/** Offset 0x02E4 +**/ + uint8_t UnusedUpdSpace12; + +/** Offset 0x02E5 - CpuS3ResumeMtrrData + Pointer CPU S3 Resume MTRR Data +**/ + uint32_t CpuS3ResumeMtrrData; + +/** Offset 0x02E9 - CpuS3ResumeMtrrDataSize + Size of S3 resume MTRR data. +**/ + uint16_t CpuS3ResumeMtrrDataSize; + +/** Offset 0x02EB +**/ + uint8_t UnusedUpdSpace13[2]; + +/** Offset 0x02ED - Cpu Configuration + Size of S3 resume MTRR data. +**/ + union CPU_CONFIG_FSP_DATA CpuConfig; + +/** Offset 0x02F9 +**/ + uint16_t UnusedUpdSpace14; + +/** Offset 0x02FB - Enable SkyCam PortA Termination override + Enable/disable PortA Termination override. + $EN_DIS +**/ + uint8_t PchSkyCamPortATermOvrEnable; + +/** Offset 0x02FC - Enable SkyCam PortB Termination override + Enable/disable PortB Termination override. + $EN_DIS +**/ + uint8_t PchSkyCamPortBTermOvrEnable; + +/** Offset 0x02FD - Enable SkyCam PortC Termination override + Enable/disable PortC Termination override. + $EN_DIS +**/ + uint8_t PchSkyCamPortCTermOvrEnable; + +/** Offset 0x02FE - Enable SkyCam PortD Termination override + Enable/disable PortD Termination override. + $EN_DIS +**/ + uint8_t PchSkyCamPortDTermOvrEnable; + +/** Offset 0x02FF - Enable SkyCam PortA Clk Trim + Enable/disable PortA Clk Trim. + $EN_DIS +**/ + uint8_t PchSkyCamPortATrimEnable; + +/** Offset 0x0300 - Enable SkyCam PortB Clk Trim + Enable/disable PortB Clk Trim. + $EN_DIS +**/ + uint8_t PchSkyCamPortBTrimEnable; + +/** Offset 0x0301 - Enable SkyCam PortC Clk Trim + Enable/disable PortC Clk Trim. + $EN_DIS +**/ + uint8_t PchSkyCamPortCTrimEnable; + +/** Offset 0x0302 - Enable SkyCam PortD Clk Trim + Enable/disable PortD Clk Trim. + $EN_DIS +**/ + uint8_t PchSkyCamPortDTrimEnable; + +/** Offset 0x0303 - Enable SkyCam PortA Ctle + Enable/disable PortA Ctle. + $EN_DIS +**/ + uint8_t PchSkyCamPortACtleEnable; + +/** Offset 0x0304 - Enable SkyCam PortB Ctle + Enable/disable PortB Ctle. + $EN_DIS +**/ + uint8_t PchSkyCamPortBCtleEnable; + +/** Offset 0x0305 - Enable SkyCam PortCD Ctle + Enable/disable PortCD Ctle. + $EN_DIS +**/ + uint8_t PchSkyCamPortCDCtleEnable; + +/** Offset 0x0306 - Enable SkyCam PortA Ctle Cap Value + Enable/disable PortA Ctle Cap Value. +**/ + uint8_t PchSkyCamPortACtleCapValue; + +/** Offset 0x0307 - Enable SkyCam PortB Ctle Cap Value + Enable/disable PortB Ctle Cap Value. +**/ + uint8_t PchSkyCamPortBCtleCapValue; + +/** Offset 0x0308 - Enable SkyCam PortCD Ctle Cap Value + Enable/disable PortCD Ctle Cap Value. +**/ + uint8_t PchSkyCamPortCDCtleCapValue; + +/** Offset 0x0309 - Enable SkyCam PortA Ctle Res Value + Enable/disable PortA Ctle Res Value. +**/ + uint8_t PchSkyCamPortACtleResValue; + +/** Offset 0x030A - Enable SkyCam PortB Ctle Res Value + Enable/disable PortB Ctle Res Value. +**/ + uint8_t PchSkyCamPortBCtleResValue; + +/** Offset 0x030B - Enable SkyCam PortCD Ctle Res Value + Enable/disable PortCD Ctle Res Value. +**/ + uint8_t PchSkyCamPortCDCtleResValue; + +/** Offset 0x030C - Enable SkyCam PortA Clk Trim Value + Enable/disable PortA Clk Trim Value. +**/ + uint8_t PchSkyCamPortAClkTrimValue; + +/** Offset 0x030D - Enable SkyCam PortB Clk Trim Value + Enable/disable PortB Clk Trim Value. +**/ + uint8_t PchSkyCamPortBClkTrimValue; + +/** Offset 0x030E - Enable SkyCam PortC Clk Trim Value + Enable/disable PortC Clk Trim Value. +**/ + uint8_t PchSkyCamPortCClkTrimValue; + +/** Offset 0x030F - Enable SkyCam PortD Clk Trim Value + Enable/disable PortD Clk Trim Value. +**/ + uint8_t PchSkyCamPortDClkTrimValue; + +/** Offset 0x0310 - Enable SkyCam Port A Data Trim Value + Enable/disable Port A Data Trim Value. +**/ + uint16_t PchSkyCamPortADataTrimValue; + +/** Offset 0x0312 - Enable SkyCam Port B Data Trim Value + Enable/disable Port B Data Trim Value. +**/ + uint16_t PchSkyCamPortBDataTrimValue; + +/** Offset 0x0314 - Enable SkyCam C/D Data Trim Value + Enable/disable C/D Data Trim Value. +**/ + uint16_t PchSkyCamPortCDDataTrimValue; + +/** Offset 0x0316 - Enable DMI ASPM + ASPM on PCH side of the DMI Link. + $EN_DIS +**/ + uint8_t PchDmiAspm; + +/** Offset 0x0317 - Enable Power Optimizer + Enable DMI Power Optimizer on PCH side. + $EN_DIS +**/ + uint8_t PchPwrOptEnable; + +/** Offset 0x0318 - PCH Flash Protection Ranges Write Enble + Write or erase is blocked by hardware. +**/ + uint8_t PchWriteProtectionEnable[5]; + +/** Offset 0x031D - PCH Flash Protection Ranges Read Enble + Read is blocked by hardware. +**/ + uint8_t PchReadProtectionEnable[5]; + +/** Offset 0x0322 - PCH Protect Range Limit + Left shifted address by 12 bits with address bits 11:0 are assumed to be FFFh for + limit comparison. +**/ + uint16_t PchProtectedRangeLimit[5]; + +/** Offset 0x032C - PCH Protect Range Base + Left shifted address by 12 bits with address bits 11:0 are assumed to be 0. +**/ + uint16_t PchProtectedRangeBase[5]; + +/** Offset 0x0336 - Enable Pme + Enable Azalia wake-on-ring. + $EN_DIS +**/ + uint8_t PchHdaPme; + +/** Offset 0x0337 - IO Buffer Voltage + I/O Buffer Voltage Mode Select: 0: 3.3V, 1: 1.8V. +**/ + uint8_t PchHdaIoBufferVoltage; + +/** Offset 0x0338 - VC Type + Virtual Channel Type Select: 0: VC0, 1: VC1. +**/ + uint8_t PchHdaVcType; + +/** Offset 0x0339 - HD Audio Link Frequency + HDA Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 0: 6MHz, , 1: 12MHz, 2: 24MHz. +**/ + uint8_t PchHdaLinkFrequency; + +/** Offset 0x033A - iDisp-Link Frequency + iDisp-Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 4: 96MHz, 3: 48MHz. +**/ + uint8_t PchHdaIDispLinkFrequency; + +/** Offset 0x033B - iDisp-Link T-mode + iDisp-Link T-Mode (PCH_HDAUDIO_IDISP_TMODE enum): 0: 2T, 1: 1T. +**/ + uint8_t PchHdaIDispLinkTmode; + +/** Offset 0x033C - Universal Audio Architecture compliance for DSP enabled system + 0: Not-UAA Compliant (Intel SST driver supported only), 1: UAA Compliant (HDA Inbox + driver or SST driver supported). + $EN_DIS +**/ + uint8_t PchHdaDspUaaCompliance; + +/** Offset 0x033D - iDisplay Audio Codec disconnection + 0: Not disconnected, enumerable, 1: Disconnected SDI, not enumerable. + $EN_DIS +**/ + uint8_t PchHdaIDispCodecDisconnect; + +/** Offset 0x033E - DSP DMIC Select (PCH_HDAUDIO_DMIC_TYPE enum) + 0: Disable; 1: 2ch array; 2: 4ch array; 3: 1ch array. +**/ + uint8_t PchHdaDspEndpointDmic; + +/** Offset 0x033F - DSP Bluetooth enablement + 0: Disable; 1: Enable. + $EN_DIS +**/ + uint8_t PchHdaDspEndpointBluetooth; + +/** Offset 0x0340 - DSP I2S enablement + 0: Disable; 1: Enable. + $EN_DIS +**/ + uint8_t PchHdaDspEndpointI2s; + +/** Offset 0x0341 - Bitmask of supported DSP features + [BIT0] - WoV; [BIT1] - BT Sideband; [BIT2] - Codec VAD; [BIT5] - BT Intel HFP; [BIT6] + - BT Intel A2DP; [BIT7] - DSP based speech pre-processing disabled; [BIT8] - 0: + Intel WoV, 1: Windows Voice Activation. +**/ + uint32_t PchHdaDspFeatureMask; + +/** Offset 0x0345 - Bitmask of supported DSP Pre/Post-Processing Modules + Deprecated: Specific pre/post-processing module bit position must be coherent with + the ACPI implementation: \_SB.PCI0.HDAS._DSM Function 3: Query Pre/Post Processing + Module Support. +**/ + uint32_t PchHdaDspPpModuleMask; + +/** Offset 0x0349 - Enable PCH Io Apic + Set to 1 if BDF value is valid. + $EN_DIS +**/ + uint8_t PchIoApicBdfValid; + +/** Offset 0x034A - PCH Io Apic Bus Number + Bus/Device/Function used as Requestor / Completer ID. Default is 0xF0. +**/ + uint8_t PchIoApicBusNumber; + +/** Offset 0x034B - PCH Io Apic Device Number + Bus/Device/Function used as Requestor / Completer ID. Default is 0x1F. +**/ + uint8_t PchIoApicDeviceNumber; + +/** Offset 0x034C - PCH Io Apic Function Number + Bus/Device/Function used as Requestor / Completer ID. Default is 0x00. +**/ + uint8_t PchIoApicFunctionNumber; + +/** Offset 0x034D - Enable PCH Io Apic Entry 24-119 + 0: Disable; 1: Enable. + $EN_DIS +**/ + uint8_t PchIoApicEntry24_119; + +/** Offset 0x034E - PCH Io Apic ID + This member determines IOAPIC ID. Default is 0x02. +**/ + uint8_t PchIoApicId; + +/** Offset 0x034F - PCH Io Apic Range Select + Define address bits 19:12 for the IOxAPIC range. Default is 0. +**/ + uint8_t PchIoApicRangeSelect; + +/** Offset 0x0350 - Enable PCH ISH SPI GPIO pins assigned + 0: Disable; 1: Enable. + $EN_DIS +**/ + uint8_t PchIshSpiGpioAssign; + +/** Offset 0x0351 - Enable PCH ISH UART0 GPIO pins assigned + 0: Disable; 1: Enable. + $EN_DIS +**/ + uint8_t PchIshUart0GpioAssign; + +/** Offset 0x0352 - Enable PCH ISH UART1 GPIO pins assigned + 0: Disable; 1: Enable. + $EN_DIS +**/ + uint8_t PchIshUart1GpioAssign; + +/** Offset 0x0353 - Enable PCH ISH I2C0 GPIO pins assigned + 0: Disable; 1: Enable. + $EN_DIS +**/ + uint8_t PchIshI2c0GpioAssign; + +/** Offset 0x0354 - Enable PCH ISH I2C1 GPIO pins assigned + 0: Disable; 1: Enable. + $EN_DIS +**/ + uint8_t PchIshI2c1GpioAssign; + +/** Offset 0x0355 - Enable PCH ISH I2C2 GPIO pins assigned + 0: Disable; 1: Enable. + $EN_DIS +**/ + uint8_t PchIshI2c2GpioAssign; + +/** Offset 0x0356 - Enable PCH ISH GP_0 GPIO pin assigned + 0: Disable; 1: Enable. + $EN_DIS +**/ + uint8_t PchIshGp0GpioAssign; + +/** Offset 0x0357 - Enable PCH ISH GP_1 GPIO pin assigned + 0: Disable; 1: Enable. + $EN_DIS +**/ + uint8_t PchIshGp1GpioAssign; + +/** Offset 0x0358 - Enable PCH ISH GP_2 GPIO pin assigned + 0: Disable; 1: Enable. + $EN_DIS +**/ + uint8_t PchIshGp2GpioAssign; + +/** Offset 0x0359 - Enable PCH ISH GP_3 GPIO pin assigned + 0: Disable; 1: Enable. + $EN_DIS +**/ + uint8_t PchIshGp3GpioAssign; + +/** Offset 0x035A - Enable PCH ISH GP_4 GPIO pin assigned + 0: Disable; 1: Enable. + $EN_DIS +**/ + uint8_t PchIshGp4GpioAssign; + +/** Offset 0x035B - Enable PCH ISH GP_5 GPIO pin assigned + 0: Disable; 1: Enable. + $EN_DIS +**/ + uint8_t PchIshGp5GpioAssign; + +/** Offset 0x035C - Enable PCH ISH GP_6 GPIO pin assigned + 0: Disable; 1: Enable. + $EN_DIS +**/ + uint8_t PchIshGp6GpioAssign; + +/** Offset 0x035D - Enable PCH ISH GP_7 GPIO pin assigned + 0: Disable; 1: Enable. + $EN_DIS +**/ + uint8_t PchIshGp7GpioAssign; + +/** Offset 0x035E - PCH ISH PDT Unlock Msg + 0: False; 1: True. + $EN_DIS +**/ + uint8_t PchIshPdtUnlock; + +/** Offset 0x035F - Enable PCH Lan LTR capabilty of PCH internal LAN + 0: Disable; 1: Enable. + $EN_DIS +**/ + uint8_t PchLanLtrEnable; + +/** Offset 0x0360 - Enable PCH Lan use CLKREQ for GbE power management + 0: Disable; 1: Enable. + $EN_DIS +**/ + uint8_t PchLanK1OffEnable; + +/** Offset 0x0361 - Indicate whether dedicated CLKREQ# is supported + 0: Disable; 1: Enable. + $EN_DIS +**/ + uint8_t PchLanClkReqSupported; + +/** Offset 0x0362 - CLKREQ# used by GbE + Valid if ClkReqSupported is TRUE. +**/ + uint8_t PchLanClkReqNumber; + +/** Offset 0x0363 - Enable LOCKDOWN BIOS LOCK + Enable the BIOS Lock feature and set EISS bit (D31:F5:RegDCh[5]) for the BIOS region + protection. + $EN_DIS +**/ + uint8_t PchLockDownBiosLock; + +/** Offset 0x0364 - Enable LOCKDOWN SPI Eiss + Enable InSMM.STS (EISS) in SPI. + $EN_DIS +**/ + uint8_t PchLockDownSpiEiss; + +/** Offset 0x0365 - PCH Sub system vendor ID + Default Subsystem Vendor ID of the PCH devices. Default is 0x8086. +**/ + uint16_t PchSubSystemVendorId; + +/** Offset 0x0367 - PCH Sub system ID + Default Subsystem ID of the PCH devices. Default is 0x7270. +**/ + uint16_t PchSubSystemId; + +/** Offset 0x0369 - PCH Compatibility Revision ID + This member describes whether or not the CRID feature of PCH should be enabled. + $EN_DIS +**/ + uint8_t PchCrid; + +/** Offset 0x036A +**/ + uint8_t UnusedUpdSpace15[6]; + +/** Offset 0x0370 - Enable PCIE RP HotPlug + Indicate whether the root port is hot plug available. +**/ + uint8_t PcieRpHotPlug[24]; + +/** Offset 0x0388 - Enable PCIE RP Pm Sci + Indicate whether the root port power manager SCI is enabled. +**/ + uint8_t PcieRpPmSci[24]; + +/** Offset 0x03A0 - Enable PCIE RP Ext Sync + Indicate whether the extended synch is enabled. +**/ + uint8_t PcieRpExtSync[24]; + +/** Offset 0x03B8 - Enable PCIE RP Transmitter Half Swing + Indicate whether the Transmitter Half Swing is enabled. +**/ + uint8_t PcieRpTransmitterHalfSwing[24]; + +/** Offset 0x03D0 - Enable PCIE RP Clk Req Detect + Probe CLKREQ# signal before enabling CLKREQ# based power management. +**/ + uint8_t PcieRpClkReqDetect[24]; + +/** Offset 0x03E8 - PCIE RP Advanced Error Report + Indicate whether the Advanced Error Reporting is enabled. +**/ + uint8_t PcieRpAdvancedErrorReporting[24]; + +/** Offset 0x0400 - PCIE RP Unsupported Request Report + Indicate whether the Unsupported Request Report is enabled. +**/ + uint8_t PcieRpUnsupportedRequestReport[24]; + +/** Offset 0x0418 - PCIE RP Fatal Error Report + Indicate whether the Fatal Error Report is enabled. +**/ + uint8_t PcieRpFatalErrorReport[24]; + +/** Offset 0x0430 - PCIE RP No Fatal Error Report + Indicate whether the No Fatal Error Report is enabled. +**/ + uint8_t PcieRpNoFatalErrorReport[24]; + +/** Offset 0x0448 - PCIE RP Correctable Error Report + Indicate whether the Correctable Error Report is enabled. +**/ + uint8_t PcieRpCorrectableErrorReport[24]; + +/** Offset 0x0460 - PCIE RP System Error On Fatal Error + Indicate whether the System Error on Fatal Error is enabled. +**/ + uint8_t PcieRpSystemErrorOnFatalError[24]; + +/** Offset 0x0478 - PCIE RP System Error On Non Fatal Error + Indicate whether the System Error on Non Fatal Error is enabled. +**/ + uint8_t PcieRpSystemErrorOnNonFatalError[24]; + +/** Offset 0x0490 - PCIE RP System Error On Correctable Error + Indicate whether the System Error on Correctable Error is enabled. +**/ + uint8_t PcieRpSystemErrorOnCorrectableError[24]; + +/** Offset 0x04A8 - PCIE RP Max Payload + Max Payload Size supported, Default 128B, see enum PCH_PCIE_MAX_PAYLOAD. +**/ + uint8_t PcieRpMaxPayload[24]; + +/** Offset 0x04C0 - PCIE RP Device Reset Pad Active High + Indicated whether PERST# is active 0: Low; 1: High, See: DeviceResetPad. +**/ + uint8_t PcieRpDeviceResetPadActiveHigh[24]; + +/** Offset 0x04D8 - PCIE RP Pcie Speed + Determines each PCIE Port speed capability. 0: Auto; 1: Gen1; 2: Gen2; 3: Gen3 (see: + PCH_PCIE_SPEED). +**/ + uint8_t PcieRpPcieSpeed[24]; + +/** Offset 0x04F0 - PCIE RP Gen3 Equalization Phase Method + PCIe Gen3 Eq Ph3 Method (see PCH_PCIE_EQ_METHOD). 0: Default; 2: Software Search; + 4: Fixed Coeficients. +**/ + uint8_t PcieRpGen3EqPh3Method[24]; + +/** Offset 0x0508 - PCIE RP Physical Slot Number + Indicates the slot number for the root port. Default is the value as root port index. +**/ + uint8_t PcieRpPhysicalSlotNumber[24]; + +/** Offset 0x0520 - PCIE RP Completion Timeout + The root port completion timeout(see: PCH_PCIE_COMPLETION_TIMEOUT). Default is PchPcieCompletionTO_Default. +**/ + uint8_t PcieRpCompletionTimeout[24]; + +/** Offset 0x0538 - PCIE RP Device Reset Pad + The PCH pin assigned to device PERST# signal if available, zero otherwise. See + also DeviceResetPadActiveHigh. +**/ + uint32_t PcieRpDeviceResetPad[24]; + +/** Offset 0x0598 - PCIE RP Aspm + The ASPM configuration of the root port (see: PCH_PCIE_ASPM_CONTROL). Default is + PchPcieAspmAutoConfig. +**/ + uint8_t PcieRpAspm[24]; + +/** Offset 0x05B0 - PCIE RP L1 Substates + The L1 Substates configuration of the root port (see: PCH_PCIE_L1SUBSTATES_CONTROL). + Default is PchPcieL1SubstatesL1_1_2. +**/ + uint8_t PcieRpL1Substates[24]; + +/** Offset 0x05C8 - PCIE RP Ltr Enable + Latency Tolerance Reporting Mechanism. +**/ + uint8_t PcieRpLtrEnable[24]; + +/** Offset 0x05E0 - PCIE RP Ltr Config Lock + 0: Disable; 1: Enable. +**/ + uint8_t PcieRpLtrConfigLock[24]; + +/** Offset 0x05F8 - PCIE Eq Ph3 Lane Param Cm + PCH_PCIE_EQ_LANE_PARAM. Coefficient C-1. +**/ + uint8_t PcieEqPh3LaneParamCm[24]; + +/** Offset 0x0610 - PCIE Eq Ph3 Lane Param Cp + PCH_PCIE_EQ_LANE_PARAM. Coefficient C+1. +**/ + uint8_t PcieEqPh3LaneParamCp[24]; + +/** Offset 0x0628 - PCIE Sw Eq CoeffList Cm + PCH_PCIE_EQ_PARAM. Coefficient C-1. +**/ + uint8_t PcieSwEqCoeffListCm[5]; + +/** Offset 0x062D - PCIE Sw Eq CoeffList Cp + PCH_PCIE_EQ_PARAM. Coefficient C+1. +**/ + uint8_t PcieSwEqCoeffListCp[5]; + +/** Offset 0x0632 - PCIE Disable RootPort Clock Gating + Describes whether the PCI Express Clock Gating for each root port is enabled by + platform modules. 0: Disable; 1: Enable. + $EN_DIS +**/ + uint8_t PcieDisableRootPortClockGating; + +/** Offset 0x0633 - PCIE Enable Peer Memory Write + This member describes whether Peer Memory Writes are enabled on the platform. + $EN_DIS +**/ + uint8_t PcieEnablePeerMemoryWrite; + +/** Offset 0x0634 - PCIE Allow No Ltr Icc PLL Shutdown + Allows BIOS to control ICC PLL Shutdown by determining PCIe devices are LTR capable + or leaving untouched. + $EN_DIS +**/ + uint8_t PcieAllowNoLtrIccPllShutdown; + +/** Offset 0x0635 - PCIE Compliance Test Mode + Compliance Test Mode shall be enabled when using Compliance Load Board. + $EN_DIS +**/ + uint8_t PcieComplianceTestMode; + +/** Offset 0x0636 - PCIE Rp Function Swap + Allows BIOS to use root port function number swapping when root port of function + 0 is disabled. + $EN_DIS +**/ + uint8_t PcieRpFunctionSwap; + +/** Offset 0x0637 - PCIE Rp Detect Timeout Ms + Will wait for link to exit Detect state for enabled ports before assuming there + is no device and potentially disabling the port. +**/ + uint16_t PcieDetectTimeoutMs; + +/** Offset 0x0639 - PCH Pm PME_B0_S5_DIS + When cleared (default), wake events from PME_B0_STS are allowed in S5 if PME_B0_EN = 1. + $EN_DIS +**/ + uint8_t PchPmPmeB0S5Dis; + +/** Offset 0x063A +**/ + uint8_t UnusedUpdSpace16[6]; + +/** Offset 0x0640 - PCH Pm Wol Enable Override + Corresponds to the WOL Enable Override bit in the General PM Configuration B (GEN_PMCON_B) register. + $EN_DIS +**/ + uint8_t PchPmWolEnableOverride; + +/** Offset 0x0641 - PCH Pm Pcie Wake From DeepSx + Determine if enable PCIe to wake from deep Sx. + $EN_DIS +**/ + uint8_t PchPmPcieWakeFromDeepSx; + +/** Offset 0x0642 - PCH Pm WoW lan Enable + Determine if WLAN wake from Sx, corresponds to the HOST_WLAN_PP_EN bit in the PWRM_CFG3 register. + $EN_DIS +**/ + uint8_t PchPmWoWlanEnable; + +/** Offset 0x0643 - PCH Pm WoW lan DeepSx Enable + Determine if WLAN wake from DeepSx, corresponds to the DSX_WLAN_PP_EN bit in the + PWRM_CFG3 register. + $EN_DIS +**/ + uint8_t PchPmWoWlanDeepSxEnable; + +/** Offset 0x0644 - PCH Pm Lan Wake From DeepSx + Determine if enable LAN to wake from deep Sx. + $EN_DIS +**/ + uint8_t PchPmLanWakeFromDeepSx; + +/** Offset 0x0645 - PCH Pm Deep Sx Pol + Deep Sx Policy. + $EN_DIS +**/ + uint8_t PchPmDeepSxPol; + +/** Offset 0x0646 - PCH Pm Slp S3 Min Assert + SLP_S3 Minimum Assertion Width Policy. Default is PchSlpS350ms. +**/ + uint8_t PchPmSlpS3MinAssert; + +/** Offset 0x0647 - PCH Pm Slp S4 Min Assert + SLP_S4 Minimum Assertion Width Policy. Default is PchSlpS44s. +**/ + uint8_t PchPmSlpS4MinAssert; + +/** Offset 0x0648 - PCH Pm Slp Sus Min Assert + SLP_SUS Minimum Assertion Width Policy. Default is PchSlpSus4s. +**/ + uint8_t PchPmSlpSusMinAssert; + +/** Offset 0x0649 - PCH Pm Slp A Min Assert + SLP_A Minimum Assertion Width Policy. Default is PchSlpA2s. +**/ + uint8_t PchPmSlpAMinAssert; + +/** Offset 0x064A +**/ + uint8_t UnusedUpdSpace17[6]; + +/** Offset 0x0650 - PCH Pm Lpc Clock Run + This member describes whether or not the LPC ClockRun feature of PCH should be enabled. + $EN_DIS +**/ + uint8_t PchPmLpcClockRun; + +/** Offset 0x0651 - PCH Pm Slp Strch Sus Up + Enable SLP_X Stretching After SUS Well Power Up. + $EN_DIS +**/ + uint8_t PchPmSlpStrchSusUp; + +/** Offset 0x0652 - PCH Pm Slp Lan Low Dc + Enable/Disable SLP_LAN# Low on DC Power. + $EN_DIS +**/ + uint8_t PchPmSlpLanLowDc; + +/** Offset 0x0653 - PCH Pm Pwr Btn Override Period + PCH power button override period. 000b-4s, 001b-6s, 010b-8s, 011b-10s, 100b-12s, 101b-14s. +**/ + uint8_t PchPmPwrBtnOverridePeriod; + +/** Offset 0x0654 - PCH Pm Disable Dsx Ac Present Pulldown + When Disable, PCH will internal pull down AC_PRESENT in deep SX and during G3 exit. + $EN_DIS +**/ + uint8_t PchPmDisableDsxAcPresentPulldown; + +/** Offset 0x0655 - PCH Pm Capsule Reset Type + Deprecated: Determines type of reset issued during UpdateCapsule(). Always Warm reset. + $EN_DIS +**/ + uint8_t PchPmCapsuleResetType; + +/** Offset 0x0656 - PCH Pm Disable Native Power Button + Power button native mode disable. + $EN_DIS +**/ + uint8_t PchPmDisableNativePowerButton; + +/** Offset 0x0657 - PCH Pm Slp S0 Enable + Indicates whether SLP_S0# is to be asserted when PCH reaches idle state. + $EN_DIS +**/ + uint8_t PchPmSlpS0Enable; + +/** Offset 0x0658 - PCH Pm ME_WAKE_STS + Clear the ME_WAKE_STS bit in the Power and Reset Status (PRSTS) register. + $EN_DIS +**/ + uint8_t PchPmMeWakeSts; + +/** Offset 0x0659 - PCH Pm WOL_OVR_WK_STS + Clear the WOL_OVR_WK_STS bit in the Power and Reset Status (PRSTS) register. + $EN_DIS +**/ + uint8_t PchPmWolOvrWkSts; + +/** Offset 0x065A - PCH Pm Reset Power Cycle Duration + Could be customized in the unit of second. Please refer to EDS for all support settings. + 0 is default, 1 is 1 second, 2 is 2 seconds, ... +**/ + uint8_t PchPmPwrCycDur; + +/** Offset 0x065B - PCH Pm Pcie Pll Ssc + Specifies the Pcie Pll Spread Spectrum Percentage. The default is 0xFF: AUTO - No + BIOS override. +**/ + uint8_t PchPmPciePllSsc; + +/** Offset 0x065C - PCH Pm WOL_OVR_WK_STS + Clear the WOL_OVR_WK_STS bit in the Power and Reset Status (PRSTS) register. + $EN_DIS +**/ + uint8_t PchPort61hEnable; + +/** Offset 0x065D - PCH Sata Pwr Opt Enable + SATA Power Optimizer on PCH side. + $EN_DIS +**/ + uint8_t SataPwrOptEnable; + +/** Offset 0x065E - PCH Sata eSATA Speed Limit + When enabled, BIOS will configure the PxSCTL.SPD to 2 to limit the eSATA port speed. + $EN_DIS +**/ + uint8_t EsataSpeedLimit; + +/** Offset 0x065F - PCH Sata Speed Limit + Indicates the maximum speed the SATA controller can support 0h: PchSataSpeedDefault. +**/ + uint8_t SataSpeedLimit; + +/** Offset 0x0660 - Enable SATA Port HotPlug + Enable SATA Port HotPlug. +**/ + uint8_t SataPortsHotPlug[8]; + +/** Offset 0x0668 - Enable SATA Port Interlock Sw + Enable SATA Port Interlock Sw. +**/ + uint8_t SataPortsInterlockSw[8]; + +/** Offset 0x0670 - Enable SATA Port External + Enable SATA Port External. +**/ + uint8_t SataPortsExternal[8]; + +/** Offset 0x0678 - Enable SATA Port SpinUp + Enable the COMRESET initialization Sequence to the device. +**/ + uint8_t SataPortsSpinUp[8]; + +/** Offset 0x0680 - Enable SATA Port Solid State Drive + 0: HDD; 1: SSD. +**/ + uint8_t SataPortsSolidStateDrive[8]; + +/** Offset 0x0688 - Enable SATA Port Enable Dito Config + Enable DEVSLP Idle Timeout settings (DmVal, DitoVal). +**/ + uint8_t SataPortsEnableDitoConfig[8]; + +/** Offset 0x0690 - Enable SATA Port DmVal + DITO multiplier. Default is 15. +**/ + uint8_t SataPortsDmVal[8]; + +/** Offset 0x0698 - Enable SATA Port DmVal + DEVSLP Idle Timeout (DITO), Default is 625. +**/ + uint16_t SataPortsDitoVal[8]; + +/** Offset 0x06A8 - Enable SATA Port ZpOdd + Support zero power ODD. +**/ + uint8_t SataPortsZpOdd[8]; + +/** Offset 0x06B0 - PCH Sata Rst Raid Alternate Id + Enable RAID Alternate ID. + $EN_DIS +**/ + uint8_t SataRstRaidAlternateId; + +/** Offset 0x06B1 - PCH Sata Rst Raid0 + RAID0. + $EN_DIS +**/ + uint8_t SataRstRaid0; + +/** Offset 0x06B2 - PCH Sata Rst Raid1 + RAID1. + $EN_DIS +**/ + uint8_t SataRstRaid1; + +/** Offset 0x06B3 - PCH Sata Rst Raid10 + RAID10. + $EN_DIS +**/ + uint8_t SataRstRaid10; + +/** Offset 0x06B4 - PCH Sata Rst Raid5 + RAID5. + $EN_DIS +**/ + uint8_t SataRstRaid5; + +/** Offset 0x06B5 - PCH Sata Rst Irrt + Intel Rapid Recovery Technology. + $EN_DIS +**/ + uint8_t SataRstIrrt; + +/** Offset 0x06B6 - PCH Sata Rst Orom Ui Banner + OROM UI and BANNER. + $EN_DIS +**/ + uint8_t SataRstOromUiBanner; + +/** Offset 0x06B7 - PCH Sata Rst Orom Ui Delay + 00b: 2 secs; 01b: 4 secs; 10b: 6 secs; 11: 8 secs (see: PCH_SATA_OROM_DELAY). +**/ + uint8_t SataRstOromUiDelay; + +/** Offset 0x06B8 - PCH Sata Rst Hdd Unlock + Indicates that the HDD password unlock in the OS is enabled. + $EN_DIS +**/ + uint8_t SataRstHddUnlock; + +/** Offset 0x06B9 - PCH Sata Rst Led Locate + Indicates that the LED/SGPIO hardware is attached and ping to locate feature is + enabled on the OS. + $EN_DIS +**/ + uint8_t SataRstLedLocate; + +/** Offset 0x06BA - PCH Sata Rst Irrt Only + Allow only IRRT drives to span internal and external ports. + $EN_DIS +**/ + uint8_t SataRstIrrtOnly; + +/** Offset 0x06BB - PCH Sata Rst Smart Storage + RST Smart Storage caching Bit. + $EN_DIS +**/ + uint8_t SataRstSmartStorage; + +/** Offset 0x06BC - PCH Sata Rst Pcie Storage Remap enable + Enable Intel RST for PCIe Storage remapping. +**/ + uint8_t SataRstPcieEnable[3]; + +/** Offset 0x06BF - PCH Sata Rst Pcie Storage Port + Intel RST for PCIe Storage remapping - PCIe Port Selection (1-based, 0 = autodetect). +**/ + uint8_t SataRstPcieStoragePort[3]; + +/** Offset 0x06C2 - PCH Sata Rst Pcie Device Reset Delay + PCIe Storage Device Reset Delay in milliseconds. Default value is 100ms +**/ + uint8_t SataRstPcieDeviceResetDelay[3]; + +/** Offset 0x06C5 - Enable eMMC HS400 Training + Determine if HS400 Training is required. + $EN_DIS +**/ + uint8_t PchScsEmmcHs400TuningRequired; + +/** Offset 0x06C6 - Set HS400 Tuning Data Valid + Set if HS400 Tuning Data Valid. + $EN_DIS +**/ + uint8_t PchScsEmmcHs400DllDataValid; + +/** Offset 0x06C7 - Rx Strobe Delay Control + Rx Strobe Delay Control - Rx Strobe Delay DLL 1 (HS400 Mode). +**/ + uint8_t PchScsEmmcHs400RxStrobeDll1; + +/** Offset 0x06C8 - Tx Data Delay Control + Tx Data Delay Control 1 - Tx Data Delay (HS400 Mode). +**/ + uint8_t PchScsEmmcHs400TxDataDll; + +/** Offset 0x06C9 - I/O Driver Strength + I/O driver strength: 0 - 33 Ohm, 1 - 40 Ohm, 2 - 50 Ohm. +**/ + uint8_t PchScsEmmcHs400DriverStrength; + +/** Offset 0x06CA - Enable Pch Serial IO GPIO + Determines if enable Serial IO GPIO. + $EN_DIS +**/ + uint8_t SerialIoGpio; + +/** Offset 0x06CB - IO voltage for I2C controllers + Selects the IO voltage for I2C controllers, 0: PchSerialIoIs33V, 1: PchSerialIoIs18V. +**/ + uint8_t SerialIoI2cVoltage[6]; + +/** Offset 0x06D1 - SPI ChipSelect signal polarity + Selects SPI ChipSelect signal polarity. +**/ + uint8_t SerialIoSpiCsPolarity[2]; + +/** Offset 0x06D3 - Enables UART hardware flow control, CTS and RTS lines + Enables UART hardware flow control, CTS and RTS linesh. +**/ + uint8_t SerialIoUartHwFlowCtrl[3]; + +/** Offset 0x06D6 - UART Number For Debug Purpose + UART number for debug purpose. 0:UART0, 1: UART1, 2:UART2. +**/ + uint8_t SerialIoDebugUartNumber; + +/** Offset 0x06D7 - Enable Debug UART Controller + Enable debug UART controller after post. +**/ + uint8_t SerialIoEnableDebugUartAfterPost; + +/** Offset 0x06D8 - Enable Serial IRQ + Determines if enable Serial IRQ. + $EN_DIS +**/ + uint8_t PchSirqEnable; + +/** Offset 0x06D9 - Serial IRQ Mode Select + Serial IRQ Mode Select, 0: quiet mode, 1: continuous mode. + $EN_DIS +**/ + uint8_t PchSirqMode; + +/** Offset 0x06DA - Start Frame Pulse Width + Start Frame Pulse Width, 0: PchSfpw4Clk, 1: PchSfpw6Clk, 2: PchSfpw8Clk. +**/ + uint8_t PchStartFramePulse; + +/** Offset 0x06DB - Enable Thermal Device + Enable Thermal Device. + $EN_DIS +**/ + uint8_t PchThermalDeviceEnable; + +/** Offset 0x06DC - Thermal Device SMI Enable + This locks down SMI Enable on Alert Thermal Sensor Trip. + $EN_DIS +**/ + uint8_t PchTsmicLock; + +/** Offset 0x06DD - Thermal Throttling Custimized T0Level Value + Custimized T0Level value. +**/ + uint16_t PchT0Level; + +/** Offset 0x06DF - Thermal Throttling Custimized T1Level Value + Custimized T1Level value. +**/ + uint16_t PchT1Level; + +/** Offset 0x06E1 - Thermal Throttling Custimized T2Level Value + Custimized T2Level value. +**/ + uint16_t PchT2Level; + +/** Offset 0x06E3 - Enable The Thermal Throttle + Enable the thermal throttle function. + $EN_DIS +**/ + uint8_t PchTTEnable; + +/** Offset 0x06E4 - PMSync State 13 + When set to 1 and the programmed GPIO pin is a 1, then PMSync state 13 will force + at least T2 state. + $EN_DIS +**/ + uint8_t PchTTState13Enable; + +/** Offset 0x06E5 - Thermal Throttle Lock + Thermal Throttle Lock. + $EN_DIS +**/ + uint8_t PchTTLock; + +/** Offset 0x06E6 - Thermal Throttling Suggested Setting + Thermal Throttling Suggested Setting. + $EN_DIS +**/ + uint8_t TTSuggestedSetting; + +/** Offset 0x06E7 - Enable PCH Cross Throttling + Enable/Disable PCH Cross Throttling + $EN_DIS +**/ + uint8_t TTCrossThrottling; + +/** Offset 0x06E8 - DMI Thermal Sensor Autonomous Width Enable + DMI Thermal Sensor Autonomous Width Enable. + $EN_DIS +**/ + uint8_t PchDmiTsawEn; + +/** Offset 0x06E9 - DMI Thermal Sensor Suggested Setting + DMT thermal sensor suggested representative values. + $EN_DIS +**/ + uint8_t DmiSuggestedSetting; + +/** Offset 0x06EA - Thermal Sensor 0 Target Width + Thermal Sensor 0 Target Width. +**/ + uint8_t DmiTS0TW; + +/** Offset 0x06EB - Thermal Sensor 1 Target Width + Thermal Sensor 1 Target Width. +**/ + uint8_t DmiTS1TW; + +/** Offset 0x06EC - Thermal Sensor 2 Target Width + Thermal Sensor 2 Target Width. +**/ + uint8_t DmiTS2TW; + +/** Offset 0x06ED - Thermal Sensor 3 Target Width + Thermal Sensor 3 Target Width. +**/ + uint8_t DmiTS3TW; + +/** Offset 0x06EE - Port 0 T1 Multipler + Port 0 T1 Multipler. +**/ + uint8_t SataP0T1M; + +/** Offset 0x06EF - Port 0 T2 Multipler + Port 0 T2 Multipler. +**/ + uint8_t SataP0T2M; + +/** Offset 0x06F0 - Port 0 T3 Multipler + Port 0 T3 Multipler. +**/ + uint8_t SataP0T3M; + +/** Offset 0x06F1 - Port 0 Tdispatch + Port 0 Tdispatch. +**/ + uint8_t SataP0TDisp; + +/** Offset 0x06F2 - Port 1 T1 Multipler + Port 1 T1 Multipler. +**/ + uint8_t SataP1T1M; + +/** Offset 0x06F3 - Port 1 T2 Multipler + Port 1 T2 Multipler. +**/ + uint8_t SataP1T2M; + +/** Offset 0x06F4 - Port 1 T3 Multipler + Port 1 T3 Multipler. +**/ + uint8_t SataP1T3M; + +/** Offset 0x06F5 - Port 1 Tdispatch + Port 1 Tdispatch. +**/ + uint8_t SataP1TDisp; + +/** Offset 0x06F6 - Port 0 Tinactive + Port 0 Tinactive. +**/ + uint8_t SataP0Tinact; + +/** Offset 0x06F7 - Port 0 Alternate Fast Init Tdispatch + Port 0 Alternate Fast Init Tdispatch. + $EN_DIS +**/ + uint8_t SataP0TDispFinit; + +/** Offset 0x06F8 - Port 1 Tinactive + Port 1 Tinactive. +**/ + uint8_t SataP1Tinact; + +/** Offset 0x06F9 - Port 1 Alternate Fast Init Tdispatch + Port 1 Alternate Fast Init Tdispatch. + $EN_DIS +**/ + uint8_t SataP1TDispFinit; + +/** Offset 0x06FA - Sata Thermal Throttling Suggested Setting + Sata Thermal Throttling Suggested Setting. + $EN_DIS +**/ + uint8_t SataThermalSuggestedSetting; + +/** Offset 0x06FB - Enable Memory Thermal Throttling + Enable Memory Thermal Throttling. + $EN_DIS +**/ + uint8_t PchMemoryThrottlingEnable; + +/** Offset 0x06FC - Memory Thermal Throttling + Enable Memory Thermal Throttling. +**/ + uint8_t PchMemoryPmsyncEnable[2]; + +/** Offset 0x06FE - Enable Memory Thermal Throttling + Enable Memory Thermal Throttling. +**/ + uint8_t PchMemoryC0TransmitEnable[2]; + +/** Offset 0x0700 - Enable Memory Thermal Throttling + Enable Memory Thermal Throttling. +**/ + uint8_t PchMemoryPinSelection[2]; + +/** Offset 0x0702 - Thermal Device Temperature + Decides the temperature. +**/ + uint16_t PchTemperatureHotLevel; + +/** Offset 0x0704 - Disable XHCI Compliance Mode + This policy will disable XHCI compliance mode on all ports. Complicance Mode should + be default enabled. + $EN_DIS +**/ + uint8_t PchDisableComplianceMode; + +/** Offset 0x0705 - USB2 Port Over Current Pin + Describe the specific over current pin number of USB 2.0 Port N. +**/ + uint8_t Usb2OverCurrentPin[16]; + +/** Offset 0x0715 - USB3 Port Over Current Pin + Describe the specific over current pin number of USB 3.0 Port N. +**/ + uint8_t Usb3OverCurrentPin[10]; + +/** Offset 0x071F - Enable 8254 Static Clock Gating in early POST time + Set 8254CGE=1 is required for C11 support. However, set 8254CGE=1 in POST time might + fail to boot legacy OS which using 8254 timer. Make sure it won't break legacy + OS boot before enabling this. + $EN_DIS +**/ + uint8_t Early8254ClockGatingEnable; + +/** Offset 0x0720 +**/ + uint32_t UnusedUpdSpace18; + +/** Offset 0x0724 - Pch PCIE device override table pointer + The PCIe device table is being used to override PCIe device ASPM settings. This + is a pointer points to a 32bit address. And it's only used in PostMem phase. Please + refer to PCH_PCIE_DEVICE_OVERRIDE structure for the table. Last entry VendorId + must be 0. +**/ + uint32_t PchPcieDeviceOverrideTablePtr; + +/** Offset 0x0728 - Enable TCO timer. + When FALSE, it disables PCH ACPI timer, and stops TCO timer. NOTE: This will have + huge power impact when it's enabled. If TCO timer is disabled, uCode ACPI timer + emulation must be enabled, and WDAT table must not be exposed to the OS. + $EN_DIS +**/ + uint8_t EnableTcoTimer; + +/** Offset 0x0729 - BgpdtHash[4] + BgpdtHash values +**/ + uint64_t BgpdtHash[4]; + +/** Offset 0x0749 - BiosGuardAttr + BiosGuardAttr default values +**/ + uint32_t BiosGuardAttr; + +/** Offset 0x074D - BiosGuardModulePtr + BiosGuardModulePtr default values +**/ + uint64_t BiosGuardModulePtr; + +/** Offset 0x0755 - SendEcCmd + SendEcCmd function pointer. \n + @code typedef EFI_STATUS (EFIAPI *PLATFORM_SEND_EC_COMMAND) (IN EC_COMMAND_TYPE + EcCmdType, IN UINT8 EcCmd, IN UINT8 SendData, IN OUT UINT8 *ReceiveData); @endcode +**/ + uint64_t SendEcCmd; + +/** Offset 0x075D - EcCmdProvisionEav + Ephemeral Authorization Value default values. Provisions an ephemeral shared secret to the EC +**/ + uint8_t EcCmdProvisionEav; + +/** Offset 0x075E - EcCmdLock + EcCmdLock default values. Locks Ephemeral Authorization Value sent previously +**/ + uint8_t EcCmdLock; + +/** Offset 0x075F - SgxEpoch0 + SgxEpoch0 default values +**/ + uint64_t SgxEpoch0; + +/** Offset 0x0767 - SgxEpoch1 + SgxEpoch1 default values +**/ + uint64_t SgxEpoch1; + +/** Offset 0x076F - SgxSinitNvsData + SgxSinitNvsData default values +**/ + uint8_t SgxSinitNvsData; + +/** Offset 0x0770 +**/ + uint8_t ReservedFspsUpd[13]; +} __attribute__((packed)); + +/** Fsp S Test Configuration +**/ +struct FSP_S_TEST_CONFIG { + +/** Offset 0x077D +**/ + uint32_t Signature; + +/** Offset 0x0781 - Enable/Disable Device 7 + Enable: Device 7 enabled, Disable (Default): Device 7 disabled + $EN_DIS +**/ + uint8_t ChapDeviceEnable; + +/** Offset 0x0782 - Skip PAM regsiter lock + Enable: PAM register will not be locked by RC, platform code should lock it, Disable(Default): + PAM registers will be locked by RC + $EN_DIS +**/ + uint8_t SkipPamLock; + +/** Offset 0x0783 - EDRAM Test Mode + Enable: PAM register will not be locked by RC, platform code should lock it, Disable(Default): + PAM registers will be locked by RC + 0: EDRAM SW disable, 1: EDRAM SW Enable, 2: EDRAM HW mode +**/ + uint8_t EdramTestMode; + +/** Offset 0x0784 - DMI Extended Sync Control + Enable: Enable DMI Extended Sync Control, Disable(Default): Disable DMI Extended + Sync Control + $EN_DIS +**/ + uint8_t DmiExtSync; + +/** Offset 0x0785 - DMI IOT Control + Enable: Enable DMI IOT Control, Disable(Default): Disable DMI IOT Control + $EN_DIS +**/ + uint8_t DmiIot; + +/** Offset 0x0786 - PEG Max Payload size per root port + 0xFF(Default):Auto, 0x1: Force 128B, 0X2: Force 256B + 0xFF: Auto, 0x1: Force 128B, 0x2: Force 256B +**/ + uint8_t PegMaxPayload[3]; + +/** Offset 0x0789 - Enable/Disable IGFX RenderStandby + Enable(Default): Enable IGFX RenderStandby, Disable: Disable IGFX RenderStandby + $EN_DIS +**/ + uint8_t RenderStandby; + +/** Offset 0x078A - Enable/Disable IGFX PmSupport + Enable(Default): Enable IGFX PmSupport, Disable: Disable IGFX PmSupport + $EN_DIS +**/ + uint8_t PmSupport; + +/** Offset 0x078B - Enable/Disable CdynmaxClamp + Enable(Default): Enable CdynmaxClamp, Disable: Disable CdynmaxClamp + $EN_DIS +**/ + uint8_t CdynmaxClampEnable; + +/** Offset 0x078C - Disable VT-d + 0=Enable/FALSE(VT-d disabled), 1=Disable/TRUE (VT-d enabled) + $EN_DIS +**/ + uint8_t VtdDisable; + +/** Offset 0x078D - GT Frequency Limit + 0xFF: Auto(Default), 6: 300 Mhz, 7: 350 Mhz, 8: 400 Mhz, 9: 450 Mhz, 0xA: 500 Mhz, + 0xB: 550 Mhz, 0xC: 600 Mhz, 0xD: 650 Mhz, 0xE: 700 Mhz, 0xF: 750 Mhz, 0x10: 800 + Mhz, 0x11: 850 Mhz, 0x12:900 Mhz, 0x13: 950 Mhz, 0x14: 1000 Mhz, 0x15: 1050 Mhz, + 0x16: 1100 Mhz, 0x17: 1150 Mhz, 0x18: 1200 Mhz + 0xFF: Auto(Default), 6: 300 Mhz, 7: 350 Mhz, 8: 400 Mhz, 9: 450 Mhz, 0xA: 500 Mhz, + 0xB: 550 Mhz, 0xC: 600 Mhz, 0xD: 650 Mhz, 0xE: 700 Mhz, 0xF: 750 Mhz, 0x10: 800 + Mhz, 0x11: 850 Mhz, 0x12:900 Mhz, 0x13: 950 Mhz, 0x14: 1000 Mhz, 0x15: 1050 Mhz, + 0x16: 1100 Mhz, 0x17: 1150 Mhz, 0x18: 1200 Mhz +**/ + uint8_t GtFreqMax; + +/** Offset 0x078E - SaPostMemTestRsvd + Reserved for SA Post-Mem Test + $EN_DIS +**/ + uint8_t SaPostMemTestRsvd[12]; + +/** Offset 0x079A +**/ + uint16_t UnusedUpdSpace19; + +/** Offset 0x079C - 1-Core Ratio Limit + 1-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused + 1-Core Ratio Limit + OC Bins.This 1-Core Ratio Limit Must be greater than or equal + to 2-Core Ratio Limit, 3-Core Ratio Limit, 4-Core Ratio Limit. Range is 0 to 83 + 0x0:0xFF +**/ + uint8_t OneCoreRatioLimit; + +/** Offset 0x079D - 2-Core Ratio Limit + 2-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused + 2-Core Ratio Limit + OC Bins.This 2-Core Ratio Limit Must be Less than or equal + to 1-Core Ratio Limit.Range is 0 to 83 + 0x0:0xFF +**/ + uint8_t TwoCoreRatioLimit; + +/** Offset 0x079E - 3-Core Ratio Limit + 3-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused + 3-Core Ratio Limit + OC Bins.This 3-Core Ratio Limit Must be Less than or equal + to 1-Core Ratio Limit.Range is 0 to 83 + 0x0:0xFF +**/ + uint8_t ThreeCoreRatioLimit; + +/** Offset 0x079F - 4-Core Ratio Limit + 4-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused + 4-Core Ratio Limit + OC Bins.This 4-Core Ratio Limit Must be Less than or equal + to 1-Core Ratio Limit.Range is 0 to 83 + 0x0:0xFF +**/ + uint8_t FourCoreRatioLimit; + +/** Offset 0x07A0 +**/ + uint8_t UnusedUpdSpace20; + +/** Offset 0x07A1 - Enable or Disable HWP + Enable or Disable HWP(Hardware P states) Support. 0: Disable; <b>1: Enable;</b> + 2-3:Reserved + $EN_DIS +**/ + uint8_t Hwp; + +/** Offset 0x07A2 - Hardware Duty Cycle Control + Hardware Duty Cycle Control configuration. 0: Disabled; <b>1: Enabled</b> 2-3:Reserved + $EN_DIS +**/ + uint8_t HdcControl; + +/** Offset 0x07A3 - Package Long duration turbo mode time + Package Long duration turbo mode time window in seconds. Valid values(Unit in seconds) + 0 to 8 , 10 , 12 ,14 , 16 , 20 , 24 , 28 , 32 , 40 , 48 , 56 , 64 , 80 , 96 , 112 , 128 + 0x0:0xFF +**/ + uint8_t PowerLimit1Time; + +/** Offset 0x07A4 - Short Duration Turbo Mode + Enable or Disable short duration Turbo Mode. </b>0 : Disable; <b>1: Enable</b> + $EN_DIS +**/ + uint8_t PowerLimit2; + +/** Offset 0x07A5 - Turbo settings Lock + Lock all Turbo settings Enable/Disable; <b>0: Disable , </b> 1: Enable + $EN_DIS +**/ + uint8_t TurboPowerLimitLock; + +/** Offset 0x07A6 - Package PL3 time window + Package PL3 time window range for this policy in milliseconds. Valid values are + 0, 3 to 8, 10, 12, 14, 16, 20 , 24, 28, 32, 40, 48, 55, 56, 64 + 0x0:0xFF +**/ + uint8_t PowerLimit3Time; + +/** Offset 0x07A7 - Package PL3 Duty Cycle + Package PL3 Duty Cycle; Valid Range is 0 to 100 + 0x0:0xFF +**/ + uint8_t PowerLimit3DutyCycle; + +/** Offset 0x07A8 - Package PL3 Lock + Package PL3 Lock Enable/Disable; <b>0: Disable ; <b> 1: Enable + $EN_DIS +**/ + uint8_t PowerLimit3Lock; + +/** Offset 0x07A9 - Package PL4 Lock + Package PL4 Lock Enable/Disable; <b>0: Disable ; <b>1: Enable + $EN_DIS +**/ + uint8_t PowerLimit4Lock; + +/** Offset 0x07AA - TCC Activation Offset + TCC Activation Offset. Offset from factory set TCC activation temperature at which + the Thermal Control Circuit must be activated. TCC will be activated at TCC Activation + Temperature, in volts.For SKL Y SKU, the recommended default for this policy is + <b>10</b>, For all other SKUs the recommended default are <b>0</b> + 0x0:0xFF +**/ + uint8_t TccActivationOffset; + +/** Offset 0x07AB - Tcc Offset Clamp Enable/Disable + Tcc Offset Clamp for Runtime Average Temperature Limit (RATL) allows CPU to throttle + below P1.For SKL Y SKU, the recommended default for this policy is <b>1: Enabled</b>, + For all other SKUs the recommended default are <b>0: Disabled</b>. + $EN_DIS +**/ + uint8_t TccOffsetClamp; + +/** Offset 0x07AC - Tcc Offset Lock + Tcc Offset Lock for Runtime Average Temperature Limit (RATL) to lock temperature + target; <b>0: Disabled</b>; 1: Enabled. + $EN_DIS +**/ + uint8_t TccOffsetLock; + +/** Offset 0x07AD - Custom Ratio State Entries + The number of custom ratio state entries, ranges from 0 to 40 for a valid custom + ratio table.Sets the number of custom P-states. At least 2 states must be present + 0x0:0xFF +**/ + uint8_t NumberOfEntries; + +/** Offset 0x07AE - Custom Short term Power Limit time window + Short term Power Limit time window value for custom CTDP level 1. Valid Range 0 to 128 + 0x0:0xFF +**/ + uint8_t Custom1PowerLimit1Time; + +/** Offset 0x07AF - Custom Turbo Activation Ratio + Turbo Activation Ratio for custom cTDP level 1. Valid Range 0 to 255 + 0x0:0xFF +**/ + uint8_t Custom1TurboActivationRatio; + +/** Offset 0x07B0 - Custom Config Tdp Control + Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2 + 0x0:0xFF +**/ + uint8_t Custom1ConfigTdpControl; + +/** Offset 0x07B1 - Custom Short term Power Limit time window + Short term Power Limit time window value for custom CTDP level 2. Valid Range 0 to 128 + 0x0:0xFF +**/ + uint8_t Custom2PowerLimit1Time; + +/** Offset 0x07B2 - Custom Turbo Activation Ratio + Turbo Activation Ratio for custom cTDP level 2. Valid Range 0 to 255 + 0x0:0xFF +**/ + uint8_t Custom2TurboActivationRatio; + +/** Offset 0x07B3 - Custom Config Tdp Control + Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2 + 0x0:0xFF +**/ + uint8_t Custom2ConfigTdpControl; + +/** Offset 0x07B4 - Custom Short term Power Limit time window + Short term Power Limit time window value for custom CTDP level 3. Valid Range 0 to 128 + 0x0:0xFF +**/ + uint8_t Custom3PowerLimit1Time; + +/** Offset 0x07B5 - Custom Turbo Activation Ratio + Turbo Activation Ratio for custom cTDP level 3. Valid Range 0 to 255 + 0x0:0xFF +**/ + uint8_t Custom3TurboActivationRatio; + +/** Offset 0x07B6 - Custom Config Tdp Control + Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2 + 0x0:0xFF +**/ + uint8_t Custom3ConfigTdpControl; + +/** Offset 0x07B7 - ConfigTdp mode settings Lock + Lock the ConfigTdp mode settings from runtime changes; <b>0: Disable</b>; 1: Enable + $EN_DIS +**/ + uint8_t ConfigTdpLock; + +/** Offset 0x07B8 - Load Configurable TDP SSDT + Configure whether to load Configurable TDP SSDT; <b>0: Disable</b>; 1: Enable. + $EN_DIS +**/ + uint8_t ConfigTdpBios; + +/** Offset 0x07B9 - PL1 Enable value + PL1 Enable value to limit average platform power. <b>0: Disable</b>; 1: Enable. + $EN_DIS +**/ + uint8_t PsysPowerLimit1; + +/** Offset 0x07BA - PL1 timewindow + PL1 timewindow in seconds.Valid values(Unit in seconds) 0 to 8 , 10 , 12 ,14 , 16 + , 20 , 24 , 28 , 32 , 40 , 48 , 56 , 64 , 80 , 96 , 112 , 128 + 0x0:0xFF +**/ + uint8_t PsysPowerLimit1Time; + +/** Offset 0x07BB - PL2 Enable Value + PL2 Enable activates the PL2 value to limit average platform power.<b>0: Disable</b>; + 1: Enable. + $EN_DIS +**/ + uint8_t PsysPowerLimit2; + +/** Offset 0x07BC +**/ + uint16_t UnusedUpdSpace21; + +/** Offset 0x07BE - Enable or Disable MLC Streamer Prefetcher + Enable or Disable MLC Streamer Prefetcher; 0: Disable; <b>1: Enable</b>. + $EN_DIS +**/ + uint8_t MlcStreamerPrefetcher; + +/** Offset 0x07BF - Enable or Disable MLC Spatial Prefetcher + Enable or Disable MLC Spatial Prefetcher; 0: Disable; <b>1: Enable</b> + $EN_DIS +**/ + uint8_t MlcSpatialPrefetcher; + +/** Offset 0x07C0 - Enable or Disable Monitor /MWAIT instructions + Enable or Disable Monitor /MWAIT instructions; 0: Disable; <b>1: Enable</b>. + $EN_DIS +**/ + uint8_t MonitorMwaitEnable; + +/** Offset 0x07C1 - Enable or Disable initialization of machine check registers + Enable or Disable initialization of machine check registers; 0: Disable; <b>1: Enable</b>. + $EN_DIS +**/ + uint8_t MachineCheckEnable; + +/** Offset 0x07C2 - Enable or Disable processor debug features + Enable or Disable processor debug features; <b>0: Disable</b>; 1: Enable. + $EN_DIS +**/ + uint8_t DebugInterfaceEnable; + +/** Offset 0x07C3 - Lock or Unlock debug interface features + Lock or Unlock debug interface features; 0: Disable; <b>1: Enable</b>. + $EN_DIS +**/ + uint8_t DebugInterfaceLockEnable; + +/** Offset 0x07C4 - AP Idle Manner of waiting for SIPI + AP Idle Manner of waiting for SIPI; 1: HALT loop; <b>2: MWAIT loop</b>; 3: RUN loop. + 0x0:0xFF +**/ + uint8_t ApIdleManner; + +/** Offset 0x07C5 - Settings for AP Handoff to OS + Settings for AP Handoff to OS; 1: HALT loop; <b>2: MWAIT loop</b>. + 0x0:0xFF +**/ + uint8_t ApHandoffManner; + +/** Offset 0x07C6 +**/ + uint16_t UnusedUpdSpace22; + +/** Offset 0x07C8 - Control on Processor Trace output scheme + Control on Processor Trace output scheme; <b>0: Single Range Output</b>; 1: ToPA Output. + 0x0:0xFF +**/ + uint8_t ProcTraceOutputScheme; + +/** Offset 0x07C9 - Enable or Disable Processor Trace feature + Enable or Disable Processor Trace feature; <b>0: Disable</b>; 1: Enable. + $EN_DIS +**/ + uint8_t ProcTraceEnable; + +/** Offset 0x07CA - Memory region allocation for Processor Trace + Memory region allocation for Processor Trace, Valid Values are 0 - 4KB , 0x1 - 8KB + , 0x2 - 16KB , 0x3 - 32KB , 0x4 - 64KB , 0x5 - 128KB , 0x6 - 256KB , 0x7 - 512KB + , 0x8 - 1MB , 0x9 - 2MB , 0xA - 4MB , 0xB - 8MB , 0xC - 16MB , 0xD - 32MB , 0xE + - 64MB , 0xF - 128MB , 0xFF: Disable + 0x0:0xFF +**/ + uint8_t ProcTraceMemSize; + +/** Offset 0x07CB +**/ + uint8_t UnusedUpdSpace23; + +/** Offset 0x07CC - Enable or Disable Voltage Optimization feature + Enable or Disable Voltage Optimization feature 0: Disable; <b>1: Enable</b> + $EN_DIS +**/ + uint8_t VoltageOptimization; + +/** Offset 0x07CD - Enable or Disable Intel SpeedStep Technology + Enable or Disable Intel SpeedStep Technology. 0: Disable; <b>1: Enable</b> + $EN_DIS +**/ + uint8_t Eist; + +/** Offset 0x07CE - Enable or Disable Energy Efficient P-state + Enable or Disable Energy Efficient P-state will be applied in Turbo mode. Disable; + <b>1: Enable</b> + $EN_DIS +**/ + uint8_t EnergyEfficientPState; + +/** Offset 0x07CF - Enable or Disable Energy Efficient Turbo + Enable or Disable Energy Efficient Turbo, will be applied in Turbo mode. Disable; + <b>1: Enable</b> + $EN_DIS +**/ + uint8_t EnergyEfficientTurbo; + +/** Offset 0x07D0 - Enable or Disable T states + Enable or Disable T states; <b>0: Disable</b>; 1: Enable. + $EN_DIS +**/ + uint8_t TStates; + +/** Offset 0x07D1 - Enable or Disable Bi-Directional PROCHOT# + Enable or Disable Bi-Directional PROCHOT#; 0: Disable; <b>1: Enable</b> + $EN_DIS +**/ + uint8_t BiProcHot; + +/** Offset 0x07D2 - Enable or Disable PROCHOT# signal being driven externally + Enable or Disable PROCHOT# signal being driven externally; 0: Disable; <b>1: Enable</b>. + $EN_DIS +**/ + uint8_t DisableProcHotOut; + +/** Offset 0x07D3 - Enable or Disable PROCHOT# Response + Enable or Disable PROCHOT# Response; <b>0: Disable</b>; 1: Enable. + $EN_DIS +**/ + uint8_t ProcHotResponse; + +/** Offset 0x07D4 - Enable or Disable VR Thermal Alert + Enable or Disable VR Thermal Alert; <b>0: Disable</b>; 1: Enable. + $EN_DIS +**/ + uint8_t DisableVrThermalAlert; + +/** Offset 0x07D5 - Enable or Disable Thermal Reporting + Enable or Disable Thermal Reporting through ACPI tables; 0: Disable; <b>1: Enable</b>. + $EN_DIS +**/ + uint8_t AutoThermalReporting; + +/** Offset 0x07D6 - Enable or Disable Thermal Monitor + Enable or Disable Thermal Monitor; 0: Disable; <b>1: Enable</b> + $EN_DIS +**/ + uint8_t ThermalMonitor; + +/** Offset 0x07D7 - Enable or Disable CPU power states (C-states) + Enable or Disable CPU power states (C-states). 0: Disable; <b>1: Enable</b> + $EN_DIS +**/ + uint8_t Cx; + +/** Offset 0x07D8 - Configure C-State Configuration Lock + Configure C-State Configuration Lock; 0: Disable; <b>1: Enable</b>. + $EN_DIS +**/ + uint8_t PmgCstCfgCtrlLock; + +/** Offset 0x07D9 - Enable or Disable Enhanced C-states + Enable or Disable Enhanced C-states. 0: Disable; <b>1: Enable</b> + $EN_DIS +**/ + uint8_t C1e; + +/** Offset 0x07DA - Enable or Disable Package Cstate Demotion + Enable or Disable Package Cstate Demotion. Disable; <b>1: Enable</b> + $EN_DIS +**/ + uint8_t PkgCStateDemotion; + +/** Offset 0x07DB - Enable or Disable Package Cstate UnDemotion + Enable or Disable Package Cstate UnDemotion. Disable; <b>1: Enable</b> + $EN_DIS +**/ + uint8_t PkgCStateUnDemotion; + +/** Offset 0x07DC - Enable or Disable CState-Pre wake + Enable or Disable CState-Pre wake. Disable; <b>1: Enable</b> + $EN_DIS +**/ + uint8_t CStatePreWake; + +/** Offset 0x07DD - Enable or Disable TimedMwait Support. + Enable or Disable TimedMwait Support. <b>Disable</b>; 1: Enable + $EN_DIS +**/ + uint8_t TimedMwait; + +/** Offset 0x07DE - Enable or Disable IO to MWAIT redirection + Enable or Disable IO to MWAIT redirection; <b>0: Disable</b>; 1: Enable. + $EN_DIS +**/ + uint8_t CstCfgCtrIoMwaitRedirection; + +/** Offset 0x07DF - Set the Max Pkg Cstate + Set the Max Pkg Cstate. Default set to Auto which limits the Max Pkg Cstate to deep + C-state. Valid values 0 - C0/C1 , 1 - C2 , 2 - C3 , 3 - C6 , 4 - C7 , 5 - C7S , + 6 - C8 , 7 - C9 , 8 - C10 , 254 - CPU Default , 255 - Auto + 0x0:0xFF +**/ + uint8_t PkgCStateLimit; + +/** Offset 0x07E0 - TimeUnit for C-State Latency Control0 + TimeUnit for C-State Latency Control0; Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns + , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns + 0x0:0xFF +**/ + uint8_t CstateLatencyControl0TimeUnit; + +/** Offset 0x07E1 - TimeUnit for C-State Latency Control1 + TimeUnit for C-State Latency Control1;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns + , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns + 0x0:0xFF +**/ + uint8_t CstateLatencyControl1TimeUnit; + +/** Offset 0x07E2 - TimeUnit for C-State Latency Control2 + TimeUnit for C-State Latency Control2;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns + , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns + 0x0:0xFF +**/ + uint8_t CstateLatencyControl2TimeUnit; + +/** Offset 0x07E3 - TimeUnit for C-State Latency Control3 + TimeUnit for C-State Latency Control3;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns + , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns + 0x0:0xFF +**/ + uint8_t CstateLatencyControl3TimeUnit; + +/** Offset 0x07E4 - TimeUnit for C-State Latency Control4 + TimeUnit for C-State Latency Control4;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns + , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns + 0x0:0xFF +**/ + uint8_t CstateLatencyControl4TimeUnit; + +/** Offset 0x07E5 - TimeUnit for C-State Latency Control5 + TimeUnit for C-State Latency Control5;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns + , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns + 0x0:0xFF +**/ + uint8_t CstateLatencyControl5TimeUnit; + +/** Offset 0x07E6 - Interrupt Redirection Mode Select + Interrupt Redirection Mode Select.0: Fixed priority; 1: Round robin;2: Hash vector;4: + PAIR with fixed priority;5: PAIR with round robin;6: PAIR with hash vector;7: No change. + 0x0:0xFF +**/ + uint8_t PpmIrmSetting; + +/** Offset 0x07E7 - Lock prochot configuration + Lock prochot configuration Enable/Disable; <b>0: Disable</b>; 1: Enable + $EN_DIS +**/ + uint8_t ProcHotLock; + +/** Offset 0x07E8 - Configuration for boot TDP selection + Configuration for boot TDP selection; <b>0: TDP Nominal</b>; 1: TDP Down; 2: TDP + Up;0xFF : Deactivate + 0x0:0xFF +**/ + uint8_t ConfigTdpLevel; + +/** Offset 0x07E9 - Max P-State Ratio + Max P-State Ratio , Valid Range 0 to 0x7F + 0x0:0xFFFF +**/ + uint16_t MaxRatio; + +/** Offset 0x07EB - Maximum P-state ratio to use in the custom P-state table + Maximum P-state ratio to use in the custom P-state table. NumOfCustomPStates has + valid range between 0 to 40. For no. of P-States supported(NumOfCustomPStates) + , StateRatio[NumOfCustomPStates] are configurable. Valid Range of value is 0 to 0x7F +**/ + uint16_t StateRatio[40]; + +/** Offset 0x083B - Platform Power Pmax + PCODE MMIO Mailbox: Platform Power Pmax. <b>0 - Auto</b> Specified in 1/8 Watt increments. + Range 0-1024 Watts. Value of 800 = 100W + 0x0:0xFFFF +**/ + uint16_t PsysPmax; + +/** Offset 0x083D - Interrupt Response Time Limit of C-State LatencyContol0 + Interrupt Response Time Limit of C-State LatencyContol0. Range of value 0 to 0x3FF + 0x0:0xFFFF +**/ + uint16_t CstateLatencyControl0Irtl; + +/** Offset 0x083F - Interrupt Response Time Limit of C-State LatencyContol1 + Interrupt Response Time Limit of C-State LatencyContol1.Range of value 0 to 0x3FF + 0x0:0xFFFF +**/ + uint16_t CstateLatencyControl1Irtl; + +/** Offset 0x0841 - Interrupt Response Time Limit of C-State LatencyContol2 + Interrupt Response Time Limit of C-State LatencyContol2.Range of value 0 to 0x3FF + 0x0:0xFFFF +**/ + uint16_t CstateLatencyControl2Irtl; + +/** Offset 0x0843 - Interrupt Response Time Limit of C-State LatencyContol3 + Interrupt Response Time Limit of C-State LatencyContol3.Range of value 0 to 0x3FF + 0x0:0xFFFF +**/ + uint16_t CstateLatencyControl3Irtl; + +/** Offset 0x0845 - Interrupt Response Time Limit of C-State LatencyContol4 + Interrupt Response Time Limit of C-State LatencyContol4.Range of value 0 to 0x3FF + 0x0:0xFFFF +**/ + uint16_t CstateLatencyControl4Irtl; + +/** Offset 0x0847 - Interrupt Response Time Limit of C-State LatencyContol5 + Interrupt Response Time Limit of C-State LatencyContol5.Range of value 0 to 0x3FF + 0x0:0xFFFF +**/ + uint16_t CstateLatencyControl5Irtl; + +/** Offset 0x0849 - Package Long duration turbo mode power limit + Package Long duration turbo mode power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit. + Valid Range 0 to 4095875 in Step size of 125 + 0x0:0xFFFFFFFF +**/ + uint32_t PowerLimit1; + +/** Offset 0x084D - Package Short duration turbo mode power limit + Package Short duration turbo mode power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid + Range 0 to 4095875 in Step size of 125 + 0x0:0xFFFFFFFF +**/ + uint32_t PowerLimit2Power; + +/** Offset 0x0851 - Package PL3 power limit + Package PL3 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid + Range 0 to 4095875 in Step size of 125 + 0x0:0xFFFFFFFF +**/ + uint32_t PowerLimit3; + +/** Offset 0x0855 - Package PL4 power limit + Package PL4 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid + Range 0 to 4095875 in Step size of 125 + 0x0:0xFFFFFFFF +**/ + uint32_t PowerLimit4; + +/** Offset 0x0859 - Tcc Offset Time Window for RATL + Package PL4 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid + Range 0 to 4095875 in Step size of 125 + 0x0:0xFFFFFFFF +**/ + uint32_t TccOffsetTimeWindowForRatl; + +/** Offset 0x085D - Short term Power Limit value for custom cTDP level 1 + Short term Power Limit value for custom cTDP level 1. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid + Range 0 to 4095875 in Step size of 125 + 0x0:0xFFFFFFFF +**/ + uint32_t Custom1PowerLimit1; + +/** Offset 0x0861 - Long term Power Limit value for custom cTDP level 1 + Long term Power Limit value for custom cTDP level 1. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid + Range 0 to 4095875 in Step size of 125 + 0x0:0xFFFFFFFF +**/ + uint32_t Custom1PowerLimit2; + +/** Offset 0x0865 - Short term Power Limit value for custom cTDP level 2 + Short term Power Limit value for custom cTDP level 2. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid + Range 0 to 4095875 in Step size of 125 + 0x0:0xFFFFFFFF +**/ + uint32_t Custom2PowerLimit1; + +/** Offset 0x0869 - Long term Power Limit value for custom cTDP level 2 + Long term Power Limit value for custom cTDP level 2. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid + Range 0 to 4095875 in Step size of 125 + 0x0:0xFFFFFFFF +**/ + uint32_t Custom2PowerLimit2; + +/** Offset 0x086D - Short term Power Limit value for custom cTDP level 3 + Short term Power Limit value for custom cTDP level 3. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid + Range 0 to 4095875 in Step size of 125 + 0x0:0xFFFFFFFF +**/ + uint32_t Custom3PowerLimit1; + +/** Offset 0x0871 - Long term Power Limit value for custom cTDP level 3 + Long term Power Limit value for custom cTDP level 3. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid + Range 0 to 4095875 in Step size of 125 + 0x0:0xFFFFFFFF +**/ + uint32_t Custom3PowerLimit2; + +/** Offset 0x0875 - Platform PL1 power + Platform PL1 power. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range + 0 to 4095875 in Step size of 125 + 0x0:0xFFFFFFFF +**/ + uint32_t PsysPowerLimit1Power; + +/** Offset 0x0879 - Platform PL2 power + Platform PL2 power. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range + 0 to 4095875 in Step size of 125 + 0x0:0xFFFFFFFF +**/ + uint32_t PsysPowerLimit2Power; + +/** Offset 0x087D - Race To Halt + Enable/Disable Race To Halt feature. RTH will dynamically increase CPU frequency + in order to enter pkg C-State faster to reduce overall power. (RTH is controlled + through MSR 1FC bit 20)Disable; <b>1: Enable</b> + $EN_DIS +**/ + uint8_t RaceToHalt; + +/** Offset 0x087E - ReservedCpuPostMemTest + Reserved for CPU Post-Mem Test + $EN_DIS +**/ + uint8_t ReservedCpuPostMemTest[12]; + +/** Offset 0x088A - SgxSinitDataFromTpm + SgxSinitDataFromTpm default values +**/ + uint8_t SgxSinitDataFromTpm; + +/** Offset 0x088B - End of Post message + Test, Send End of Post message. Disable(0x0): Disable EOP message, Send in PEI(0x1): + EOP send in PEI, Send in DXE(0x2)(Default): EOP send in DXE + 0:Disable, 1:Send in PEI, 2:Send in DXE, 3:Reserved +**/ + uint8_t EndOfPostMessage; + +/** Offset 0x088C - D0I3 Setting for HECI Disable + Test, 0: disable, 1: enable, Setting this option disables setting D0I3 bit for all + HECI devices + $EN_DIS +**/ + uint8_t DisableD0I3SettingForHeci; + +/** Offset 0x088D - HD Audio Reset Wait Timer + The delay timer after Azalia reset, the value is number of microseconds. Default is 600. +**/ + uint16_t PchHdaResetWaitTimer; + +/** Offset 0x088F - Enable LOCKDOWN SMI + Enable SMI_LOCK bit to prevent writes to the Global SMI Enable bit. + $EN_DIS +**/ + uint8_t PchLockDownGlobalSmi; + +/** Offset 0x0890 - Enable LOCKDOWN BIOS Interface + Enable BIOS Interface Lock Down bit to prevent writes to the Backup Control Register. + $EN_DIS +**/ + uint8_t PchLockDownBiosInterface; + +/** Offset 0x0891 - RTC CMOS RAM LOCK + Enable RTC lower and upper 128 byte Lock bits to lock Bytes 38h-3Fh in the upper + and and lower 128-byte bank of RTC RAM. + $EN_DIS +**/ + uint8_t PchLockDownRtcLock; + +/** Offset 0x0892 - PCH Sbi lock bit + This unlock the SBI lock bit to allow SBI after post time. 0: Disable; 1: Enable. + $EN_DIS +**/ + uint8_t PchSbiUnlock; + +/** Offset 0x0893 - PCH Psf lock bit + The PSF registers will be locked before 3rd party code execution. 0: Disable; 1: Enable. + $EN_DIS +**/ + uint8_t PchSbAccessUnlock; + +/** Offset 0x0894 - PCIE RP Ltr Max Snoop Latency + Latency Tolerance Reporting, Max Snoop Latency. +**/ + uint16_t PcieRpLtrMaxSnoopLatency[24]; + +/** Offset 0x08C4 - PCIE RP Ltr Max No Snoop Latency + Latency Tolerance Reporting, Max Non-Snoop Latency. +**/ + uint16_t PcieRpLtrMaxNoSnoopLatency[24]; + +/** Offset 0x08F4 - PCIE RP Snoop Latency Override Mode + Latency Tolerance Reporting, Snoop Latency Override Mode. +**/ + uint8_t PcieRpSnoopLatencyOverrideMode[24]; + +/** Offset 0x090C - PCIE RP Snoop Latency Override Multiplier + Latency Tolerance Reporting, Snoop Latency Override Multiplier. +**/ + uint8_t PcieRpSnoopLatencyOverrideMultiplier[24]; + +/** Offset 0x0924 - PCIE RP Snoop Latency Override Value + Latency Tolerance Reporting, Snoop Latency Override Value. +**/ + uint16_t PcieRpSnoopLatencyOverrideValue[24]; + +/** Offset 0x0954 - PCIE RP Non Snoop Latency Override Mode + Latency Tolerance Reporting, Non-Snoop Latency Override Mode. +**/ + uint8_t PcieRpNonSnoopLatencyOverrideMode[24]; + +/** Offset 0x096C - PCIE RP Non Snoop Latency Override Multiplier + Latency Tolerance Reporting, Non-Snoop Latency Override Multiplier. +**/ + uint8_t PcieRpNonSnoopLatencyOverrideMultiplier[24]; + +/** Offset 0x0984 - PCIE RP Non Snoop Latency Override Value + Latency Tolerance Reporting, Non-Snoop Latency Override Value. +**/ + uint16_t PcieRpNonSnoopLatencyOverrideValue[24]; + +/** Offset 0x09B4 - PCIE RP Slot Power Limit Scale + Specifies scale used for slot power limit value. Leave as 0 to set to default. +**/ + uint8_t PcieRpSlotPowerLimitScale[24]; + +/** Offset 0x09CC - PCIE RP Slot Power Limit Value + Specifies upper limit on power supplie by slot. Leave as 0 to set to default. +**/ + uint16_t PcieRpSlotPowerLimitValue[24]; + +/** Offset 0x09FC - PCIE RP Upstream Port Transmiter Preset + Used during Gen3 Link Equalization. Used for all lanes. Default is 5. +**/ + uint8_t PcieRpUptp[24]; + +/** Offset 0x0A14 - PCIE RP Downstream Port Transmiter Preset + Used during Gen3 Link Equalization. Used for all lanes. Default is 7. +**/ + uint8_t PcieRpDptp[24]; + +/** Offset 0x0A2C - PCIE RP Enable Port8xh Decode + This member describes whether PCIE root port Port 8xh Decode is enabled. 0: Disable; + 1: Enable. + $EN_DIS +**/ + uint8_t PcieEnablePort8xhDecode; + +/** Offset 0x0A2D - PCIE Port8xh Decode Port Index + The Index of PCIe Port that is selected for Port8xh Decode (0 Based). +**/ + uint8_t PchPciePort8xhDecodePortIndex; + +/** Offset 0x0A2E - PCH Pm Disable Energy Report + Disable/Enable PCH to CPU enery report feature. + $EN_DIS +**/ + uint8_t PchPmDisableEnergyReport; + +/** Offset 0x0A2F - PCH Pm Pmc Read Disable + When set to true, this bit disallows host reads to PMC XRAM. + $EN_DIS +**/ + uint8_t PchPmPmcReadDisable; + +/** Offset 0x0A30 - PCH Sata Test Mode + Allow entrance to the PCH SATA test modes. + $EN_DIS +**/ + uint8_t SataTestMode; + +/** Offset 0x0A31 +**/ + uint8_t ReservedFspsTestUpd[15]; +} __attribute__((packed)); + +/** Fsp S UPD Configuration +**/ +struct FSPS_UPD { + +/** Offset 0x0000 +**/ + struct FSP_UPD_HEADER FspUpdHeader; + +/** Offset 0x0020 +**/ + struct FSP_S_CONFIG FspsConfig; + +/** Offset 0x077D +**/ + struct FSP_S_TEST_CONFIG FspsTestConfig; + +/** Offset 0x0A40 +**/ + uint8_t UnusedUpdSpace24[474]; + +/** Offset 0x0C1A +**/ + uint16_t UpdTerminator; +} __attribute__((packed)); + +#endif |