summaryrefslogtreecommitdiff
path: root/src
diff options
context:
space:
mode:
authorSubrata Banik <subrata.banik@intel.com>2017-03-09 13:56:17 +0530
committerMartin Roth <martinroth@google.com>2017-04-10 20:40:01 +0200
commite0268d3e1a3ad1511be6c8e512582c7109794510 (patch)
treed5beced350f9a4e483b399dd2571283c71cf67ef /src
parent8e84723e02537229e079dcdb0795d2903eb1603d (diff)
downloadcoreboot-e0268d3e1a3ad1511be6c8e512582c7109794510.tar.xz
soc/intel/skylake: Use RTC common code
This patch uses common RTC library to enable upper 128 byte bank of RTC RAM. Change-Id: Ibcbaf5061e96a67815116a9f7a03be515997be6d Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/18701 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
Diffstat (limited to 'src')
-rw-r--r--src/soc/intel/skylake/Kconfig1
-rw-r--r--src/soc/intel/skylake/bootblock/pch.c12
2 files changed, 3 insertions, 10 deletions
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index ae86198935..e22f1e37a4 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -52,6 +52,7 @@ config CPU_SPECIFIC_OPTIONS
select SOC_INTEL_COMMON_BLOCK
select SOC_INTEL_COMMON_BLOCK_GSPI
select SOC_INTEL_COMMON_BLOCK_PCR
+ select SOC_INTEL_COMMON_BLOCK_RTC
select SOC_INTEL_COMMON_BLOCK_SA
select SOC_INTEL_COMMON_BLOCK_XHCI
select SOC_INTEL_COMMON_LPSS_I2C
diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c
index ebd68f1988..12ce3d00a9 100644
--- a/src/soc/intel/skylake/bootblock/pch.c
+++ b/src/soc/intel/skylake/bootblock/pch.c
@@ -19,6 +19,7 @@
#include <device/device.h>
#include <device/pci_def.h>
#include <intelblocks/pcr.h>
+#include <intelblocks/rtc.h>
#include <soc/bootblock.h>
#include <soc/iomap.h>
#include <soc/itss.h>
@@ -45,9 +46,6 @@
#define PCR_DMI_LPCIOD 0x2770
#define PCR_DMI_LPCIOE 0x2774
-#define PCR_RTC_CONF 0x3400
-#define PCR_RTC_CONF_UCMOS_EN 0x4
-
/*
* Enable Prefetching and Caching.
*/
@@ -247,12 +245,6 @@ static void soc_config_tco(void)
outw(tcocnt, tcobase + TCO1_CNT);
}
-static void soc_config_rtc(void)
-{
- /* Enable upper 128 bytes of CMOS */
- pcr_or32(PID_RTC, PCR_RTC_CONF, PCR_RTC_CONF_UCMOS_EN);
-}
-
static void enable_heci(void)
{
device_t dev = PCH_DEV_CSE;
@@ -322,7 +314,7 @@ void pch_early_init(void)
/* Set up GPE configuration */
pmc_gpe_init();
- soc_config_rtc();
+ enable_rtc_upper_bank();
enable_heci();
}