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authorHsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>2019-07-10 21:31:34 +0800
committerJulius Werner <jwerner@chromium.org>2019-08-21 18:12:15 +0000
commite804695c6a327b7e9d1ac0838dcd818520224f26 (patch)
treee48828c6d07968628ca133890dee5c116ee9140b /src
parent4c095fc9e91e68ab15d2ff256260acc9fd65dd91 (diff)
downloadcoreboot-e804695c6a327b7e9d1ac0838dcd818520224f26.tar.xz
mediatek/mt8183: add scp voltage initialization
Add scp voltage initialization. BUG=b:135985700 BRANCH=none Test=Boots correctly on Kukui and scp can boot up normally Change-Id: I5afb60af3c14490e20f28f1c089cfca42ddf7fcf Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34205 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/google/kukui/romstage.c1
-rw-r--r--src/soc/mediatek/mt8183/include/soc/mt6358.h1
-rw-r--r--src/soc/mediatek/mt8183/mt6358.c29
3 files changed, 31 insertions, 0 deletions
diff --git a/src/mainboard/google/kukui/romstage.c b/src/mainboard/google/kukui/romstage.c
index 1465243f07..a86690b6fb 100644
--- a/src/mainboard/google/kukui/romstage.c
+++ b/src/mainboard/google/kukui/romstage.c
@@ -32,6 +32,7 @@ void platform_romstage_main(void)
/* Adjust VSIM2 down to 2.7V because it is shared with IT6505. */
pmic_set_vsim2_cali(2700);
mt_pll_raise_ca53_freq(1989 * MHz);
+ pmic_init_scp_voltage();
rtc_boot();
mt_mem_init(get_sdram_config());
mtk_mmu_after_dram();
diff --git a/src/soc/mediatek/mt8183/include/soc/mt6358.h b/src/soc/mediatek/mt8183/include/soc/mt6358.h
index 277ee9aa35..19ab5e106e 100644
--- a/src/soc/mediatek/mt8183/include/soc/mt6358.h
+++ b/src/soc/mediatek/mt8183/include/soc/mt6358.h
@@ -40,5 +40,6 @@ struct pmic_setting {
void mt6358_init(void);
void pmic_set_power_hold(bool enable);
void pmic_set_vsim2_cali(unsigned int vsim2_mv);
+void pmic_init_scp_voltage(void);
#endif /* __SOC_MEDIATEK_MT6358_H__ */
diff --git a/src/soc/mediatek/mt8183/mt6358.c b/src/soc/mediatek/mt8183/mt6358.c
index 53d2a43803..fa928cbcf6 100644
--- a/src/soc/mediatek/mt8183/mt6358.c
+++ b/src/soc/mediatek/mt8183/mt6358.c
@@ -731,11 +731,40 @@ static struct pmic_setting lp_setting[] = {
{0x1DA6, 0x0, 0x1, 3},
};
+static struct pmic_setting scp_setting[] = {
+ /* scp voltage initialization */
+ /* [6:0]: RG_BUCK_VCORE_SSHUB_VOSEL */
+ {0x14A6, 0x20, 0x7F, 0},
+ /* [14:8]: RG_BUCK_VCORE_SSHUB_VOSEL_SLEEP */
+ {0x14A6, 0x20, 0x7F, 8},
+ /* [0:0]: RG_BUCK_VCORE_SSHUB_EN */
+ {0x14A4, 0x1, 0x1, 0},
+ /* [1:1]: RG_BUCK_VCORE_SSHUB_SLEEP_VOSEL_EN */
+ {0x14A4, 0x0, 0x1, 1},
+ /* [6:0]: RG_LDO_VSRAM_OTHERS_SSHUB_VOSEL */
+ {0x1BC6, 0x40, 0x7F, 0},
+ /* [14:8]: RG_LDO_VSRAM_OTHERS_SSHUB_VOSEL_SLEEP */
+ {0x1BC6, 0x40, 0x7F, 8},
+ /* [0:0]: RG_LDO_VSRAM_OTHERS_SSHUB_EN */
+ {0x1BC4, 0x1, 0x1, 0},
+ /* [1:1]: RG_LDO_VSRAM_OTHERS_SSHUB_SLEEP_VOSEL_EN */
+ {0x1BC4, 0x0, 0x1, 1},
+ /* [4:4]: RG_SRCVOLTEN_LP_EN */
+ {0x134, 0x1, 0x1, 4},
+};
void pmic_set_power_hold(bool enable)
{
pwrap_write_field(PMIC_PWRHOLD, (enable) ? 1 : 0, 0x1, 0);
}
+void pmic_init_scp_voltage(void)
+{
+ for (size_t i = 0; i < ARRAY_SIZE(scp_setting); i++)
+ pwrap_write_field(
+ scp_setting[i].addr, scp_setting[i].val,
+ scp_setting[i].mask, scp_setting[i].shift);
+}
+
void pmic_set_vsim2_cali(unsigned int vsim2_mv)
{
u16 vsim2_reg, cali_mv;