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authorJonathan A. Kollasch <jakllsch@kollasch.net>2012-01-04 19:37:48 -0600
committerMarc Jones <marcj303@gmail.com>2012-01-05 18:08:07 +0100
commitf3fe3d2140e147b7cb55428a982f14dacd0f8ef7 (patch)
tree435d9c21c0eef1a336d57bcf0b1f86a23d57426c /src
parent0786bc6ad89449f810e169c131da2047af9a7048 (diff)
downloadcoreboot-f3fe3d2140e147b7cb55428a982f14dacd0f8ef7.tar.xz
rs780: use bitwise rather than boolean not
Change-Id: Ie3872c57990f9784aafda14f8c7fc842b3a65260 Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-on: http://review.coreboot.org/518 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Marc Jones <marcj303@gmail.com>
Diffstat (limited to 'src')
-rw-r--r--src/southbridge/amd/rs780/pcie.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/southbridge/amd/rs780/pcie.c b/src/southbridge/amd/rs780/pcie.c
index efa2e58e76..be80ed3e0e 100644
--- a/src/southbridge/amd/rs780/pcie.c
+++ b/src/southbridge/amd/rs780/pcie.c
@@ -72,7 +72,7 @@ static void PciePowerOffGppPorts(device_t nb_dev, device_t dev, u32 port)
state = ~state;
state &= (1 << 4) + (1 << 5) + (1 << 6) + (1 << 7);
state_save = state << 17;
- state &= !(AtiPcieCfg.PortHp);
+ state &= ~(AtiPcieCfg.PortHp);
reg = nbmisc_read_index(nb_dev, 0x0c);
reg |= state;
nbmisc_write_index(nb_dev, 0x0c, reg);