summaryrefslogtreecommitdiff
path: root/src
diff options
context:
space:
mode:
authorKyösti Mälkki <kyosti.malkki@gmail.com>2012-07-11 14:40:19 +0300
committerRonald G. Minnich <rminnich@gmail.com>2012-07-12 20:28:35 +0200
commitffc1fb35aab659127156d4aa28c1cbd6d5793b19 (patch)
tree577bd1f9c7fe5199d0f438a225b4fd615bd11578 /src
parentdb2c400ab852a2aae09d812b20e520ca371da35b (diff)
downloadcoreboot-ffc1fb35aab659127156d4aa28c1cbd6d5793b19.tar.xz
Drop Kconfig VAR_MTRR_HOLE option
All but one board use the default value of enabled. Disabling this can only increase the number of MTRR registers used. Change-Id: I7d28adc31b9fae2301e4ff78fcb96486f81d5ec2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1213 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src')
-rw-r--r--src/cpu/Kconfig7
-rw-r--r--src/cpu/x86/mtrr/mtrr.c16
-rw-r--r--src/mainboard/msi/ms9652_fam10/Kconfig4
3 files changed, 4 insertions, 23 deletions
diff --git a/src/cpu/Kconfig b/src/cpu/Kconfig
index acb9bb5d0a..85e83d428e 100644
--- a/src/cpu/Kconfig
+++ b/src/cpu/Kconfig
@@ -61,11 +61,4 @@ config SSE2
streaming SIMD instructions. Some parts of coreboot can be built
with more efficient code if SSE2 instructions are available.
-config VAR_MTRR_HOLE
- bool
- default y
- help
- Unset this if you don't want the MTRR code to use
- subtractive MTRRs
-
endif # ARCH_X86
diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c
index f8b2591e36..f9e0716283 100644
--- a/src/cpu/x86/mtrr/mtrr.c
+++ b/src/cpu/x86/mtrr/mtrr.c
@@ -342,10 +342,6 @@ static void set_fixed_mtrr_resource(void *gp, struct device *dev, struct resourc
}
-#ifndef CONFIG_VAR_MTRR_HOLE
-#define CONFIG_VAR_MTRR_HOLE 1
-#endif
-
struct var_mtrr_state {
unsigned long range_startk, range_sizek;
unsigned int reg;
@@ -373,7 +369,6 @@ void set_var_mtrr_resource(void *gp, struct device *dev, struct resource *res)
}
/* Write the range mtrrs */
if (state->range_sizek != 0) {
-#if CONFIG_VAR_MTRR_HOLE
if (state->hole_sizek == 0 && state->above4gb != 2) {
/* We need to put that on to hole */
unsigned long endk = basek + sizek;
@@ -382,15 +377,14 @@ void set_var_mtrr_resource(void *gp, struct device *dev, struct resource *res)
state->range_sizek = endk - state->range_startk;
return;
}
-#endif
state->reg = range_to_mtrr(state->reg, state->range_startk,
state->range_sizek, basek, MTRR_TYPE_WRBACK,
state->address_bits, state->above4gb);
-#if CONFIG_VAR_MTRR_HOLE
+
state->reg = range_to_mtrr(state->reg, state->hole_startk,
state->hole_sizek, basek, MTRR_TYPE_UNCACHEABLE,
state->address_bits, state->above4gb);
-#endif
+
state->range_startk = 0;
state->range_sizek = 0;
state->hole_startk = 0;
@@ -470,25 +464,23 @@ void x86_setup_var_mtrrs(unsigned int address_bits, unsigned int above4gb)
if (var_state.hole_startk || var_state.hole_sizek) {
printk(BIOS_DEBUG, "Warning: Can't set up MTRR hole for UMA due to pre-existing MTRR hole.\n");
} else {
-#if CONFIG_VAR_MTRR_HOLE
// Increase the base range and set up UMA as an UC hole instead
if (above4gb != 2)
var_state.range_sizek += (uma_memory_size >> 10);
var_state.hole_startk = (uma_memory_base >> 10);
var_state.hole_sizek = (uma_memory_size >> 10);
-#endif
}
#endif
/* Write the last range */
var_state.reg = range_to_mtrr(var_state.reg, var_state.range_startk,
var_state.range_sizek, 0, MTRR_TYPE_WRBACK,
var_state.address_bits, var_state.above4gb);
-#if CONFIG_VAR_MTRR_HOLE
+
var_state.reg = range_to_mtrr(var_state.reg, var_state.hole_startk,
var_state.hole_sizek, 0, MTRR_TYPE_UNCACHEABLE,
var_state.address_bits, var_state.above4gb);
-#endif
+
printk(BIOS_DEBUG, "DONE variable MTRRs\n");
printk(BIOS_DEBUG, "Clear out the extra MTRR's\n");
/* Clear out the extra MTRR's */
diff --git a/src/mainboard/msi/ms9652_fam10/Kconfig b/src/mainboard/msi/ms9652_fam10/Kconfig
index a1f69c8db2..2bb4a614af 100644
--- a/src/mainboard/msi/ms9652_fam10/Kconfig
+++ b/src/mainboard/msi/ms9652_fam10/Kconfig
@@ -137,10 +137,6 @@ config SB_HT_CHAIN_ON_BUS0
int
default 1
-config VAR_MTRR_HOLE
- bool
- default n
-
config APIC_ID_OFFSET
hex
default 0x00