diff options
| author | Julien Viard de Galbert <jviarddegalbert@online.net> | 2018-03-07 14:18:49 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-01-24 14:05:10 +0000 |
| commit | 053ea606828afecbabf458beb575272dccdd8a36 (patch) | |
| tree | a71869dd48d0b49e7bfc6a821b793801a18351ea /src | |
| parent | 15b570b716ff9865fcc942a2c5a0eeeccad1fd1e (diff) | |
| download | coreboot-053ea606828afecbabf458beb575272dccdd8a36.tar.xz | |
soc/intel/denverton_ns: Configure MCA
Change-Id: I101eb4f008a13af92bac5ed738a8d1f1f8c65eba
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/c/25433
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/denverton_ns/cpu.c | 29 | ||||
| -rw-r--r-- | src/soc/intel/denverton_ns/include/soc/msr.h | 5 |
2 files changed, 34 insertions, 0 deletions
diff --git a/src/soc/intel/denverton_ns/cpu.c b/src/soc/intel/denverton_ns/cpu.c index b3a12c5cad..ce6df68f9f 100644 --- a/src/soc/intel/denverton_ns/cpu.c +++ b/src/soc/intel/denverton_ns/cpu.c @@ -35,12 +35,41 @@ static struct smm_relocation_attrs relo_attrs; +static void dnv_configure_mca(void) +{ + msr_t msr; + int num_banks; + struct cpuid_result cpuid_regs; + + /* Check feature flag in CPUID.(EAX=1):EDX[7]==1 MCE + * and CPUID.(EAX=1):EDX[14]==1 MCA*/ + cpuid_regs = cpuid(1); + if ((cpuid_regs.edx & (1<<7 | 1<<14)) != (1<<7 | 1<<14)) + return; + + msr = rdmsr(IA32_MCG_CAP); + num_banks = msr.lo & IA32_MCG_CAP_COUNT_MASK; + if (msr.lo & IA32_MCG_CAP_CTL_P_MASK) { + /* Enable all error logging */ + msr.lo = msr.hi = 0xffffffff; + wrmsr(IA32_MCG_CTL, msr); + } + + /* TODO(adurbin): This should only be done on a cold boot. Also, some + of these banks are core vs package scope. For now every CPU clears + every bank. */ + mca_configure(NULL); +} + static void denverton_core_init(struct device *cpu) { msr_t msr; printk(BIOS_DEBUG, "Init Denverton-NS SoC cores.\n"); + /* Clear out pending MCEs */ + dnv_configure_mca(); + /* Enable Fast Strings */ msr = rdmsr(IA32_MISC_ENABLE); msr.lo |= FAST_STRINGS_ENABLE_BIT; diff --git a/src/soc/intel/denverton_ns/include/soc/msr.h b/src/soc/intel/denverton_ns/include/soc/msr.h index 825d4cfca8..1b27eefcaa 100644 --- a/src/soc/intel/denverton_ns/include/soc/msr.h +++ b/src/soc/intel/denverton_ns/include/soc/msr.h @@ -25,6 +25,11 @@ #define MSR_PKG_CST_CONFIG_CONTROL 0xe2 #define MSR_PMG_IO_CAPTURE_BASE 0xe4 #define MSR_FEATURE_CONFIG 0x13c +#define IA32_MCG_CAP 0x179 +#define IA32_MCG_CAP_COUNT_MASK 0xff +#define IA32_MCG_CAP_CTL_P_BIT 8 +#define IA32_MCG_CAP_CTL_P_MASK (1 << IA32_MCG_CAP_CTL_P_BIT) +#define IA32_MCG_CTL 0x17b #define SMM_MCA_CAP_MSR 0x17d #define SMM_CPU_SVRSTR_BIT 57 #define SMM_CPU_SVRSTR_MASK (1 << (SMM_CPU_SVRSTR_BIT - 32)) |