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| author | Arthur Heymans <arthur@aheymans.xyz> | 2019-01-05 18:21:47 +0100 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-01-08 15:41:51 +0000 |
| commit | 0eb9c57049c091b767f5fe65a8c6886567b0700e (patch) | |
| tree | 6c2450b5aad2be6933ad3df1cf39d6d8db0f89d8 /src | |
| parent | ad80e7f11840ab3828cc594b212ec90bb5810986 (diff) | |
| download | coreboot-0eb9c57049c091b767f5fe65a8c6886567b0700e.tar.xz | |
arch/x86: Link walkcbfs.S instead of including it
Link walkfcbfs.S in the C_ENVIRONMENT_BOOTBLOCK case and also in the
romstage.
This is useful for cbfs access in pre-CAR environments.
Change-Id: I9a17cdf01c7cbc3c9ac45ed1f075731f3e32f64b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30681
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/arch/x86/Makefile.inc | 3 | ||||
| -rw-r--r-- | src/cpu/intel/microcode/microcode_asm.S | 7 | ||||
| -rw-r--r-- | src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S | 6 |
3 files changed, 14 insertions, 2 deletions
diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index d6f9b6b0a0..8dafac8131 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -122,6 +122,8 @@ else $(eval $(call early_x86_stage,bootblock,elf64-x86-64)) endif +bootblock-y += walkcbfs.S + else # !C_ENVIRONMENT_BOOTBLOCK # x86-specific linker flags @@ -233,6 +235,7 @@ romstage-y += memset.c romstage-$(CONFIG_X86_TOP4G_BOOTMEDIA_MAP) += mmap_boot.c romstage-y += postcar_loader.c romstage-$(CONFIG_COLLECT_TIMESTAMPS_TSC) += timestamp.c +romstage-y += walkcbfs.S romstage-srcs += $(wildcard $(src)/mainboard/$(MAINBOARDDIR)/romstage.c) romstage-libs ?= diff --git a/src/cpu/intel/microcode/microcode_asm.S b/src/cpu/intel/microcode/microcode_asm.S index ef85760269..039e02a2b7 100644 --- a/src/cpu/intel/microcode/microcode_asm.S +++ b/src/cpu/intel/microcode/microcode_asm.S @@ -20,7 +20,12 @@ #include <cpu/x86/post_code.h> #include <cpu/x86/msr.h> -#include <arch/x86/walkcbfs.S> + +#define CBFS_FILE_MAGIC 0 +#define CBFS_FILE_LEN (CBFS_FILE_MAGIC + 8) +#define CBFS_FILE_TYPE (CBFS_FILE_LEN + 4) +#define CBFS_FILE_CHECKSUM (CBFS_FILE_TYPE + 4) +#define CBFS_FILE_OFFSET (CBFS_FILE_CHECKSUM + 4) #define HEADER_VER_OFFSET 0 #define UPDATE_VER_OFFSET 4 diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S b/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S index c557a025fe..9a8ab5ba42 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S @@ -19,8 +19,12 @@ #include <cpu/x86/cache.h> #include <cpu/x86/cr.h> #include <cpu/x86/post_code.h> -#include <../../../../../arch/x86/walkcbfs.S> +#define CBFS_FILE_MAGIC 0 +#define CBFS_FILE_LEN (CBFS_FILE_MAGIC + 8) +#define CBFS_FILE_TYPE (CBFS_FILE_LEN + 4) +#define CBFS_FILE_CHECKSUM (CBFS_FILE_TYPE + 4) +#define CBFS_FILE_OFFSET (CBFS_FILE_CHECKSUM + 4) .extern temp_ram_init_params |