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authorMichael Niewöhner <foss@mniewoehner.de>2020-04-30 00:44:04 +0200
committerPatrick Georgi <pgeorgi@google.com>2020-05-04 18:52:17 +0000
commit13dee2a9113bfbcce9ae8b302a759af062ecf486 (patch)
tree85f1e4c7cfa1357e8200c87f7d2390de25cab6ee /src
parente01054d86eecfff846764e640eaafe58b5d5fb5d (diff)
downloadcoreboot-13dee2a9113bfbcce9ae8b302a759af062ecf486.tar.xz
soc/intel/skl: always enable SataPwrOptEnable
For unknown reasons FSP skips a whole bunch of SIR (SATA Initialization Registers) when SataPwrOptEnable=0, which currently is the default in coreboot and FSP. Even if FSP's default was 1, coreboot would reset it. This can lead to all sorts of problems and errors, for example: - links get lost - only 1.5 or 3 Gbps instead of 6 Gbps - "unaligned write" errors in Linux - ... At least on two boards (supermicro/x11-lga1151-series/x11ssm-f and purism/librem13v2) SATA is not working correctly and showing such symptoms. To let FSP correctly initialize the SATA controller, enable the option SataPwrOptEnable statically. There is no valid reason to disable it, which might break SATA, anyway. Currently, there are no reported issues on CML and CNL, so a change there could not be tested reliably. SKL/KBL was tested successfully without any noticable downsides. Thus, only SKL gets changed for now. Change-Id: I8531ba9743453a3118b389565517eb769b5e7929 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40877 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/51nb/x210/devicetree.cb1
-rw-r--r--src/mainboard/google/fizz/variants/baseboard/devicetree.cb1
-rw-r--r--src/mainboard/protectli/vault_kbl/devicetree.cb1
-rw-r--r--src/soc/intel/skylake/chip.c8
-rw-r--r--src/soc/intel/skylake/chip.h3
5 files changed, 7 insertions, 7 deletions
diff --git a/src/mainboard/51nb/x210/devicetree.cb b/src/mainboard/51nb/x210/devicetree.cb
index 82bbb1fc74..e453aa432f 100644
--- a/src/mainboard/51nb/x210/devicetree.cb
+++ b/src/mainboard/51nb/x210/devicetree.cb
@@ -48,7 +48,6 @@ chip soc/intel/skylake
register "SataPortsDevSlp[0]" = "1"
register "SataPortsDevSlp[1]" = "1"
register "SataPortsDevSlp[2]" = "1"
- register "SataPwrOptEnable" = "1"
register "EnableAzalia" = "1"
register "DspEnable" = "0"
register "IoBufferOwnership" = "0"
diff --git a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb
index 5da9997d59..f02accec71 100644
--- a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb
@@ -72,7 +72,6 @@ chip soc/intel/skylake
register "SataPortsEnable[0]" = "1"
register "SataPortsEnable[1]" = "1"
register "SataPortsDevSlp[1]" = "1"
- register "SataPwrOptEnable" = "1"
register "EnableAzalia" = "1"
register "DspEnable" = "1"
register "IoBufferOwnership" = "3"
diff --git a/src/mainboard/protectli/vault_kbl/devicetree.cb b/src/mainboard/protectli/vault_kbl/devicetree.cb
index d53e43eba3..d3e8b2305c 100644
--- a/src/mainboard/protectli/vault_kbl/devicetree.cb
+++ b/src/mainboard/protectli/vault_kbl/devicetree.cb
@@ -38,7 +38,6 @@ chip soc/intel/skylake
register "EnableSata" = "1"
register "SataSalpSupport" = "0"
register "SataMode" = "0"
- register "SataPwrOptEnable" = "1"
register "EnableAzalia" = "0"
register "DspEnable" = "0"
register "IoBufferOwnership" = "0"
diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c
index b731baff8d..b24ec4fdc0 100644
--- a/src/soc/intel/skylake/chip.c
+++ b/src/soc/intel/skylake/chip.c
@@ -258,9 +258,15 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
params->SataEnable = config->EnableSata;
params->SataMode = config->SataMode;
params->SataSpeedLimit = config->SataSpeedLimit;
- params->SataPwrOptEnable = config->SataPwrOptEnable;
params->EnableTcoTimer = !config->PmTimerDisabled;
+ /*
+ * For unknown reasons FSP skips writing some essential SATA init registers (SIR) when
+ * SataPwrOptEnable=0. This results in link errors, "unaligned write" errors and others.
+ * Enabling this option solves these problems.
+ */
+ params->SataPwrOptEnable = 1;
+
tconfig->PchLockDownGlobalSmi = config->LockDownConfigGlobalSmi;
tconfig->PchLockDownRtcLock = config->LockDownConfigRtcLock;
tconfig->PowerLimit4 = config->PowerLimit4;
diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h
index 387bd6fe3d..d268eebd66 100644
--- a/src/soc/intel/skylake/chip.h
+++ b/src/soc/intel/skylake/chip.h
@@ -567,9 +567,6 @@ struct soc_intel_skylake_config {
*/
u8 IslVrCmd;
- /* Enable/Disable Sata power optimization */
- u8 SataPwrOptEnable;
-
/* Enable/Disable Sata test mode */
u8 SataTestMode;