diff options
| author | Roy Mingi Park <roy.mingi.park@intel.com> | 2019-02-13 11:10:45 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-02-15 16:23:28 +0000 |
| commit | 1ac2ad0fbe8c1d7029e4f593fefe763212df6728 (patch) | |
| tree | f2fbe09fd6a2588bd692243e711ca51992b6516c /src | |
| parent | 783be13495a920502c1e2ef25cadd2d9558df013 (diff) | |
| download | coreboot-1ac2ad0fbe8c1d7029e4f593fefe763212df6728.tar.xz | |
soc/intel/cannonlake: Define VR settings
Define VR settings configuration as per board design.
BUG=N/A
TEST=Build and boot up into sarien platform.
Change-Id: Ic9927943b1f8fab687659fd1d6da0e3988a3aba2
Signed-off-by: Roy Mingi Park <roy.mingi.park@intel.com>
Reviewed-on: https://review.coreboot.org/c/31405
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/cannonlake/include/soc/vr_config.h | 2 | ||||
| -rw-r--r-- | src/soc/intel/cannonlake/vr_config.c | 49 |
2 files changed, 50 insertions, 1 deletions
diff --git a/src/soc/intel/cannonlake/include/soc/vr_config.h b/src/soc/intel/cannonlake/include/soc/vr_config.h index 385767d957..8bcf001ea9 100644 --- a/src/soc/intel/cannonlake/include/soc/vr_config.h +++ b/src/soc/intel/cannonlake/include/soc/vr_config.h @@ -55,6 +55,8 @@ struct vr_config { uint16_t dc_loadline; }; +#define VR_CFG_AMP(i) ((i) * 4) + /* VrConfig Settings for 4 domains * 0 = System Agent, 1 = IA Core, * 2 = GT unsliced, 3 = GT sliced */ diff --git a/src/soc/intel/cannonlake/vr_config.c b/src/soc/intel/cannonlake/vr_config.c index fff68c7e18..25270d8f98 100644 --- a/src/soc/intel/cannonlake/vr_config.c +++ b/src/soc/intel/cannonlake/vr_config.c @@ -19,7 +19,54 @@ #include <soc/vr_config.h> static const struct vr_config default_configs[NUM_VR_DOMAINS] = { - /* TODO: define this*/ + [VR_SYSTEM_AGENT] = { + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(6), + .voltage_limit = 1520, + }, + [VR_IA_CORE] = { + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(70), + .voltage_limit = 1520, + }, + [VR_GT_UNSLICED] = { + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(31), + .voltage_limit = 1520, + }, + [VR_GT_SLICED] = { + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(31), + .voltage_limit = 1520, + }, }; void fill_vr_domain_config(void *params, |