summaryrefslogtreecommitdiff
path: root/src
diff options
context:
space:
mode:
authorAlexander Couzens <lynxis@fe80.eu>2015-02-28 20:07:10 +0100
committerPeter Stuge <peter@stuge.se>2015-04-05 03:28:11 +0200
commit23d12329773f1dbbe43bfec3b8b0781ca62eb474 (patch)
tree4e9dac81036db865f5d78403882e628e7f30e3f6 /src
parent60d44dd0a436eee2c7f3e9cf5a572163cfbd9a80 (diff)
downloadcoreboot-23d12329773f1dbbe43bfec3b8b0781ca62eb474.tar.xz
mainboard/lenovo/x201: correct sata_port_map
x201 has 2 sata ports. 1 port for hard drive and 1 port for the dock. Tested on x201 with hdd in port 1 + cdrom in port 2. Change-Id: I1ee8c547392257d4f2e00a5d48e21447a84f79c0 Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-on: http://review.coreboot.org/8657 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/lenovo/x201/devicetree.cb2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/lenovo/x201/devicetree.cb b/src/mainboard/lenovo/x201/devicetree.cb
index ffd3addc78..402b9d4911 100644
--- a/src/mainboard/lenovo/x201/devicetree.cb
+++ b/src/mainboard/lenovo/x201/devicetree.cb
@@ -99,7 +99,7 @@ chip northbridge/intel/nehalem
register "gpi1_routing" = "2"
register "gpi13_routing" = "2"
- register "sata_port_map" = "0x33"
+ register "sata_port_map" = "0x03"
register "gpe0_en" = "0x20022046"
register "alt_gp_smi_en" = "0x0000"