diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-09-16 13:29:21 +0200 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2020-10-24 20:42:32 +0000 |
| commit | 2f30e8ca03602c14fd98527f1ea54d2a80e4fd63 (patch) | |
| tree | 7a9822acb3e6e78e9dec4d758ed54d81d538a70b /src | |
| parent | ae2a5228277f3c5b00c29e6f9567ced67309f064 (diff) | |
| download | coreboot-2f30e8ca03602c14fd98527f1ea54d2a80e4fd63.tar.xz | |
nb/intel/gm45: Clean up header handling
There's no need to have ACPI guards in `gm45.h`, since the only things
the ASL files require are the base address definitions in `memmap.h`.
Also, remove the southbridge include from `gm45.h` and place it only in
the files that actually require something from it.
Tested with BUILD_TIMELESS=1, Roda RK9 remains identical.
Change-Id: Ica2c5ae9f57595c8577a1bfcc3b57f2c57b3e980
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45452
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/northbridge/intel/gm45/acpi/gm45.asl | 3 | ||||
| -rw-r--r-- | src/northbridge/intel/gm45/early_init.c | 1 | ||||
| -rw-r--r-- | src/northbridge/intel/gm45/gm45.h | 9 | ||||
| -rw-r--r-- | src/northbridge/intel/gm45/pcie.c | 1 |
4 files changed, 4 insertions, 10 deletions
diff --git a/src/northbridge/intel/gm45/acpi/gm45.asl b/src/northbridge/intel/gm45/acpi/gm45.asl index af58e0e712..e4d8d66993 100644 --- a/src/northbridge/intel/gm45/acpi/gm45.asl +++ b/src/northbridge/intel/gm45/acpi/gm45.asl @@ -1,7 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include "hostbridge.asl" -#include "../gm45.h" +#include "../memmap.h" +#include <southbridge/intel/i82801ix/i82801ix.h> #include <southbridge/intel/common/rcba.h> /* PCI Device Resource Consumption */ diff --git a/src/northbridge/intel/gm45/early_init.c b/src/northbridge/intel/gm45/early_init.c index e362841fb3..86f71d6ff8 100644 --- a/src/northbridge/intel/gm45/early_init.c +++ b/src/northbridge/intel/gm45/early_init.c @@ -2,6 +2,7 @@ #include <stdint.h> #include <device/pci_ops.h> +#include <southbridge/intel/i82801ix/i82801ix.h> #include "gm45.h" void gm45_early_init(void) diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h index 8be18733d1..4d8a923c57 100644 --- a/src/northbridge/intel/gm45/gm45.h +++ b/src/northbridge/intel/gm45/gm45.h @@ -3,10 +3,6 @@ #ifndef __NORTHBRIDGE_INTEL_GM45_GM45_H__ #define __NORTHBRIDGE_INTEL_GM45_GM45_H__ -#include <southbridge/intel/i82801ix/i82801ix.h> - -#ifndef __ACPI__ - #include <stdint.h> typedef enum { @@ -163,8 +159,6 @@ enum { VCO_5333 = 2, }; -#endif - /* Offsets of read/write training results in CMOS. They will be restored upon S3 resumes. */ #define CMOS_READ_TRAINING 0x80 /* 16 bytes */ @@ -409,8 +403,6 @@ enum { #define EP_PORTARB(x) (0x100 + 4 * (x)) /* 256bit */ -#ifndef __ACPI__ - void gm45_early_init(void); void gm45_early_reset(void); @@ -460,5 +452,4 @@ struct acpi_rsdp; unsigned long northbridge_write_acpi_tables(const struct device *device, unsigned long start, struct acpi_rsdp *rsdp); -#endif /* !__ACPI__ */ #endif /* __NORTHBRIDGE_INTEL_GM45_GM45_H__ */ diff --git a/src/northbridge/intel/gm45/pcie.c b/src/northbridge/intel/gm45/pcie.c index ce49d6200d..fd7ce527a1 100644 --- a/src/northbridge/intel/gm45/pcie.c +++ b/src/northbridge/intel/gm45/pcie.c @@ -4,6 +4,7 @@ #include <device/pci_ops.h> #include <device/pci_def.h> #include <console/console.h> +#include <southbridge/intel/i82801ix/i82801ix.h> #include "gm45.h" |