diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2017-07-10 13:17:09 +0530 |
|---|---|---|
| committer | Duncan Laurie <dlaurie@chromium.org> | 2017-07-12 04:00:41 +0000 |
| commit | 3214bc4ecca20bb44aa9a94f164c7fb4feb76c0b (patch) | |
| tree | 4b71cc01671c31f60fe333f254540d6205c16633 /src | |
| parent | b5c5b9dc7cb211003d6a453167492eb25ec511c0 (diff) | |
| download | coreboot-3214bc4ecca20bb44aa9a94f164c7fb4feb76c0b.tar.xz | |
soc/intel/skylake: Remove “disable SaGv” in recovery mode flow
This reverts commit 5535cead (intel/skylake: Disable SaGv in
recovery mode).
Commit 5535cead disables SaGv in recovery mode to save few seconds
booting time as we were doing memory training on every recovery flow.
Now we don't need to perform MRC training on every recovery boot
due to RECOVERY_MRC_CACHE implementation in place. Hence we don't
need to define different SaGv policy between Normal (developer) mode
and recovery mode to save few seconds.
Using different SaGv parameters between recovery and all other mode
has some significent drawbacks over warm reboot cycle. We are seeing
a MRC traning hang in eve/soraka/poppy devices with below use case.
Step 1: Boot system in developer mode (first time RW_MRC training)
Step 2: Set recovery_request=1 (using crossystem) and issue “reboot”
from OS
Step 3: System will perform recovery mode MRC training and boot to
OS (first time RECOVERY_MRC training)
Step 4: Issue “reboot” from OS console.
Step 5: System wil boot in developer mode (using RW_MRC cache)
Step 6: Set recovery_request=1 (using crossystem) and issue “reboot”
from OS
Step 7: System will pick RECOVERY_MRC_CACHE and will hang during
MRC training.
This patch fixes issue mentioned above and ensures system boot to
OS without any hang if we change mode (dev<->recovery) over warm
reset.
BUG=b:63515071
BRANCH=none
TEST=manual stress testing of dev<->recovery mode over warm boot.
No MRC hang with this fix on eve/soraka/poppy devices.
Change-Id: I8d094a8b6d78ea3bf8f929870a4a179495c29c78
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/20516
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/skylake/romstage/romstage_fsp20.c | 5 |
1 files changed, 1 insertions, 4 deletions
diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c index 4530190b07..093f7c09b9 100644 --- a/src/soc/intel/skylake/romstage/romstage_fsp20.c +++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c @@ -203,10 +203,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE; m_cfg->IedSize = CONFIG_IED_REGION_SIZE; m_cfg->ProbelessTrace = config->ProbelessTrace; - if (vboot_recovery_mode_enabled()) - m_cfg->SaGv = 0; /* Disable SaGv in recovery mode. */ - else - m_cfg->SaGv = config->SaGv; + m_cfg->SaGv = config->SaGv; m_cfg->UserBd = BOARD_TYPE_ULT_ULX; m_cfg->RMT = config->Rmt; m_cfg->DdrFreqLimit = config->DdrFreqLimit; |