diff options
| author | Duncan Laurie <dlaurie@chromium.org> | 2013-09-25 14:08:32 -0700 |
|---|---|---|
| committer | Patrick Georgi <patrick@georgi-clan.de> | 2014-07-11 18:08:03 +0200 |
| commit | 32d2e2b3608006b615521eb68f011aa72f44171e (patch) | |
| tree | 683ae9fa9a7b1e70a6ad379481a25b0410d11d2c /src | |
| parent | 16a0f5c4e3677ce93949bb5383ebd04a636d13e7 (diff) | |
| download | coreboot-32d2e2b3608006b615521eb68f011aa72f44171e.tar.xz | |
intel/lynxpoint: Work around XHCI resume issues
When USB3 devices are attached while in suspend, or two USB3 devices
that are both plugged in are switched to the other port while in
suspend the kernel does not seem to notice this -- despite the cold
attach status bit. This results in the devices showing up in the USB
list at the old enumerated device numbers and higher layers continuing
to think they are present but not reseponding.
With the kernel workaround to deal with devices that are logically
disconnected it is possible for firmware to send a warm port reset to
devices that are in this state and then the kernel will see them disappear
and handle it properly.
This same issue exists in the EFI firmware on the Whitetip Mountain 2
reference board so it is not specifically a coreboot bug. If this
behavior is fixed in the kernel then this workaround could be removed
since it is in RW firmware.
BUG=chrome-os-partner:22818
BRANCH=falco,peppy,wolf,leon
TEST=manual:
1) attach two USB3 devices
2) suspend system
3) switch the ports that the USB3 devices are attatched to
4) resume system
5) confirm that the devices are re-enumerated and come up properly
Original-Change-Id: Ifba3ffc94a06dc0b2436d7d7d464d824657362af
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/170335
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 203d200268f4af6445224962190cbc66ad2a83e4)
Change-Id: I54fd2847ee25a60f25c2cefebdc1a3c18455464a
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/170579
[pm: rebase to master branch of coreboot upstream]
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/6017
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Diffstat (limited to 'src')
| -rw-r--r-- | src/southbridge/intel/lynxpoint/usb_xhci.c | 13 |
1 files changed, 10 insertions, 3 deletions
diff --git a/src/southbridge/intel/lynxpoint/usb_xhci.c b/src/southbridge/intel/lynxpoint/usb_xhci.c index e09134081c..997ef61098 100644 --- a/src/southbridge/intel/lynxpoint/usb_xhci.c +++ b/src/southbridge/intel/lynxpoint/usb_xhci.c @@ -37,8 +37,6 @@ static u32 usb_xhci_mem_base(device_t dev) return mem_base & ~0xf; } -#ifdef __SMM__ - static int usb_xhci_port_count_usb3(device_t dev) { if (pch_is_lp()) { @@ -127,7 +125,8 @@ static void usb_xhci_reset_usb3(device_t dev, int all) continue; status = read32(portsc) & XHCI_USB3_PORTSC_PLS; /* Reset all or only disconnected ports */ - if (all || status == XHCI_PLSR_RXDETECT) + if (all || (status == XHCI_PLSR_RXDETECT || + status == XHCI_PLSR_POLLING)) usb_xhci_reset_port_usb3(mem_base, port); else port_disabled |= 1 << port; @@ -156,6 +155,8 @@ static void usb_xhci_reset_usb3(device_t dev, int all) usb_xhci_reset_status_usb3(mem_base, port); } +#ifdef __SMM__ + /* Handler for XHCI controller on entry to S3/S4/S5 */ void usb_xhci_sleep_prepare(device_t dev, u8 slp_typ) { @@ -350,6 +351,12 @@ static void usb_xhci_init(device_t dev) reg32 &= ~(1 << 23); /* unsupported request */ reg32 |= (1 << 31); pci_write_config32(dev, 0x40, reg32); + + if (acpi_is_wakeup_s3()) { + /* Reset ports that are disabled or + * polling before returning to the OS. */ + usb_xhci_reset_usb3(dev, 0); + } } static void usb_xhci_set_subsystem(device_t dev, unsigned vendor, |